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CS5166GDW16 参数 Datasheet PDF下载

CS5166GDW16图片预览
型号: CS5166GDW16
PDF下载: 下载PDF文件 查看货源
内容描述: 5位同步CPU控制器与电源就绪和电流限制 [5-Bit Synchronous CPU Controller with Power-Good and Current Limit]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 22 页 / 436 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Application Information: continued  
the DC accuracy spec, the voltage drop developed across  
3) Thermal Considerations  
the resistor must be calculated as follows:  
Due to I2 × R power losses the surface temperature of  
the droop resistor will increase causing the resistance  
to increase. Also, the ambient temperature variation  
will contribute to the increase of the resistance,  
according to the formula:  
[VDAC(MIN)-VDC PENTIUM®II(MIN)  
]
VDROOP(TYP)  
=
=
1+RDROOP(TOLERANCE)  
2.796V-2.74V  
= 43mV  
1.3  
R = R20 [1+ α20(Τ−20)]  
where:  
R20 = resistance at 20˚C  
With the CS5166 DAC accuracy being 1%, the internal  
error amplifier’s reference voltage is trimmed so that the  
output voltage will be 25mV high at no load. With no load,  
there is no DC drop across the resistor, producing an out-  
put voltage tracking the error amplifier output voltage,  
including the offset. When the full load current is deliv-  
ered, a drop of -43mV is developed across the resistor.  
Therefore, the regulator output is pre-positioned at 25mV  
above the nominal output voltage before a load turn-on.  
The total voltage drop due to a load step is V-25mV and  
the deviation from the nominal output voltage is 25mV  
smaller than it would be if there was no droop resistor.  
Similarly at full load the regulator output is pre-positioned  
at 18mV below the nominal voltage before a load turn-off.  
the total voltage increase due to a load turn-off is V-18mV  
and the deviation from the nominal output voltage is  
18mV smaller than it would be if there was no droop resis-  
tor. This is because the output capacitors are pre-charged  
to value that is either 25mV above the nominal output  
voltage before a load turn-on or, 18mV below the nominal  
output voltage before a load turn-off (see Figure 8).  
0.00393  
α =  
˚C  
T= operating temperature  
R = desired droop resistor value  
For temperature T = 50˚C,  
the % R change = 12%  
Droop Resistor Tolerance  
Tolerance due to sheet resistivity variation  
Tolerance due to L/W error  
Tolerance due to temperature variation  
Total tolerance for droop resistor  
In order to determine the droop resistor value the nominal  
voltage drop across it at full load has to be calculated. This  
voltage drop has to be such that the output voltage full  
load is above the minimum DC tolerance spec.  
16%  
1%  
12%  
29%  
Obviously, the larger the voltage drop across the droop  
resistor (the larger the resistance), the worse the DC and  
load regulation, but the better the AC transient response.  
[VDAC(MIN)-VDC(MIN)  
1+RDROOP(TOLERANCE)  
]
VDROOP(TYP)  
=
Current Limit Setpoint Calculations  
The following is the design equation used to set the cur-  
rent limit trip point by determining the value of the  
embedded PCB trace used as a current sensing element.  
Example: for a 300MHz Pentium®II, the DC accuracy spec  
is 2.74 < VCC(CORE) < 2.9V, and the AC accuracy spec is  
2.67V < VCC(CORE) <2.93V. The CS5166 DAC output volt-  
age is +2.796V < VDAC < +2.853V. In order not to exceed  
The current limit setpoint has to be higher than the normal  
full load current. Attention has to be paid to the current  
VIN  
CS5166  
IFB  
RFB  
Current Limit Comparator  
V
FB  
+
-
Q1  
Q2  
I
SENSE  
L
RDROOP  
V
OUT  
VTH  
I
SENSE  
C
OUT  
RISENSE  
ISENSE  
Figure 22: Circuit used to determine the voltage across the droop resistor that will trip the internal current sense comparator.  
14