CS5165H
Absolute Maximum Ratings
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 150°C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Sec max. above 183°C, 230°C Peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65°C
to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Pin Symbol
Pin Name
V
MAX
20V
6V
6V
6V
6V
6V
20V
20V
6V
6V
0V
0V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
0V
0V
I
SOURCE
N/A
200µA
10mA
10µA
1mA
1mA
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
100µA
10µA
1.5A Peak
200mA DC
100mA
I
SINK
1.5A Peak
200mA DC
10µA
1mA
10µA
50mA
10µA
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
1mA
30mA
N/A
N/A
V
CC
SS
COMP
V
FB
C
OFF
V
ID0-4
GATE(H)
GATE(L)
ENABLE
PWRGD
PGnd
LGnd
IC Power Input
Soft Start Capacitor
Compensation Capacitor
Voltage Feedback Input
Off-Time Capacitor
Voltage ID DAC Inputs
High-Side FET Driver
Low-Side FET Driver
Enable Input
Power-Good Output
Power Ground
Logic Ground
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1,2,3,4,6
V
ID0
-V
ID4
Voltage ID DAC inputs. These pins are internally pulled up to 5V if left open.
V
ID4
selects the DAC range. When V
ID4
is high (logic one), the Error Amp ref-
erence range is 2.14V to 3.54V with 100mV increments. When V
ID4
is low (logic
zero), the Error amp reference voltage is 1.34V to 2.09V with 50mV increments.
Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and fault
timing.
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the nor-
mal and extended off time.
Output Enable Input. This pin is internally pulled up to 1.8V. A logic Low
( < 0.8V) on this pin disables operation and places the CS5165H into a low
current sleep mode.
Input Power Supply Pin.
High Side Switch FET driver pin.
High Current ground for the GATE(H) and GATE(L) pins.
Low Side Synchronous FET driver pin.
Power Good Output. Open collector output drives low when V
FB
is out of
regulation. Active when ENABLE input is low
Reference ground. All control circuits are referenced to this pin.
Error Amp output. PWM Comparator reference input. A capacitor to LGnd
provides Error Amp compensation.
Error Amp, PWM Comparator, and Low V
FB
Comparator feedback input.
5
7
8
SS
C
OFF
ENABLE
9
10
11
12
13
14
15
16
V
CC
GATE(H)
PGnd
GATE(L)
PWRGD
LGnd
COMP
V
FB
2
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
