CS5156
Applications Information: continued
area can be used to improve the power handling capability
of surface mount components.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional com-
ponents may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the cir-
cuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
This causes the output voltage to be +40mV with no load,
and -40mV with a full load, improving regulator transient
response. This trace must be wide enough to carry the full
output current. (Typical trace is 1.0 inch long, 0.17 inch
wide). Care should be taken to minimize any additional
losses after the feedback connection point to maximize reg-
ulation.
7. If DC regulation is to be optimized (at the expense of
degraded transient regulation), adaptive voltage position-
ing can be disabled by connecting to V
FB
pin directly to the
load with a separate trace (remote sense).
8. Place 5V input capacitors close to the switching MOS-
FET.
Route gate drive signal V
GATE
(pin 10) with a trace that is a
minimum of 0.025 inches wide.
V
CC
0.1µF
15
To the negative terminal of the
input capacitors
11
1.0µF
V
COMP
100pF
V
FFB
2µH
2µH
SOFTSTART
8
5
33Ω
1000pF
1200µF x 3/16V
+
OFF TIME
To the negative terminal of the output capacitors
Figure 18: Layout Guidelines
Figure 16: Filter components
Figure 17: Input Filter
Layout Guidelines
1. Place 12V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGnd).
2. Connect pin 11 (PGnd) with a separate trace to the
ground terminals of the 5V input capacitors.
3. Place fast feedback filter capacitor next to pin 8 (V
FFB
)
and connect its ground terminal with a separate, wide trace
directly to pin 14 (LGnd).
4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback filter
capacitor to prevent common mode noise from effecting
the PWM comparator.
5. Place the output filter capacitor(s) as close to the load as
possible and connect the ground terminal to pin 14 (LGnd).
6. To implement adaptive voltage positioning, connect
both slow and fast feedback pins 16 (V
FB
) and 8 (V
FFB
) to
the regulator output right at the inductor terminal. Connect
inductor to the output capacitors via a trace with the fol-
lowing resistance:
R
TRACE
=
80mV
I
MAX
12
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
