CS51312
Absolute Maximum Ratings
Operating Junction Temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature Soldering
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak
Storage Temperature Range, T
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65° to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Pin Symbol
Pin Name
V
MAX
16V
20V
6V
6V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
N/A
N/A
1mA
1mA
I
SINK
1.5A Peak
200mA
1.5A Peak
200mA
5mA
1mA
V
CC1
V
CC2
COMP
V
FB
, V
OUT
, V
ID0-4
C
OFF
GATE(H)
GATE(L)
PWRGD
OVP
Gnd
IC Bias and Low Side Driver
Power Input
IC High Side Driver Power Input
Compensation Pin
Voltage Feedback Input, Output
Voltage Sense Pin, Voltage
ID DAC Inputs
Off-Time Pin
High-Side FET Driver
Low-Side FET Driver
Power-Good Output
Overvoltage Protection
Ground
6V
20V
16V
6V
15V
0V
-0.3V
-0.3V DC
-0.3V
-0.3V
0V
1mA
50mA
1.5APeak
1.5A Peak
200mA DC 200mA DC
1mA
30mA
30mA
1mA
1.5A Peak
N/A
200mA DC
Package Pin Description
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1,2,3,4,5
V
IDO
– V
ID4
6
V
FB
V
OUT
V
CC1
V
CC2
GATE(H)
Gnd
GATE(L)
OVP
PWRGD
C
OFF
COMP
7
8
9
10
11
12
13
14
15
16
Voltage ID DAC inputs. These pins are internally pulled up to
5.65V if left open. V
ID4
selects the DAC range. When V
ID4
is
high (logic one), the Error Amp reference range is 2.125V to
3.525V with 100mV increments. When V
ID4
is low (logic zero),
the Error amp reference voltage is 1.325V to 2.075V with 50mV
increments.
Error amp inverting input, PWM comparator non-inverting
input, current limit comparator non-inverting input, PWRGD
and OVP comparator input.
Current limit comparator inverting input.
Input power supply pin for the internal circuitry and low side
gate driver. Decouple with filter capacitor to Gnd.
Input power supply pin for the high side gate driver.
Decouple with filter capacitor to Gnd.
High side switch FET driver pin .
Ground pin and IC substrate connection.
Low side synchronous FET driver pin.
Overvoltage protection pin. Drives high when overvoltage
condition is detected on V
FB
.
Power-Good Output. Open collector output drives low when
V
FB
is out of regulation.
Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets
the off time for the regulator
Error amp output. PWM comparator inverting input.
A capacitor on this pin provides error amp compensation, and
determines the Soft Start and hiccup timing. Pulling COMP
below 1.1V (typ) turns off both GATE drivers and shuts down
the regulator.
2
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
