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CS51311GD14 参数 Datasheet PDF下载

CS51311GD14图片预览
型号: CS51311GD14
PDF下载: 下载PDF文件 查看货源
内容描述: CPU同步降压控制器的12V和5V的应用 [Synchronous CPU Buck Controller for 12V and 5V Applications]
分类和应用: 开关光电二极管控制器
文件页数/大小: 19 页 / 239 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Application Information: continued  
When driving large capacitive loads, the COMP must  
Slope Compensation  
charge slowly enough to avoid tripping the CS51311 over-  
current protection. The following equation can be used to  
ensure unconditional startup:  
The V2TM control method uses a ramp signal, generated by  
the ESR of the output capacitors, that is proportional to the  
ripple current through the inductor. To maintain regulation,  
the V2TM control loop monitors this ramp signal, through the  
PWM comparator, and terminates the switch on-time.  
ICHG  
I
LIM ILOAD  
<
CCOMP  
COUT  
The stringent load transient requirements of modern  
microprocessors require the output capacitors to have very  
low ESR. The resulting shallow slope presented to the  
PWM comparator, due to the very low ESR, can lead to  
pulse width jitter and variation caused by both random or  
synchronous noise.  
where  
CHG = COMP Source Current (30µA typical);  
COMP = COMP Capacitor value (0.1µF typical);  
ILIM = Current Limit Threshold;  
LOAD = Load Current during startup;  
OUT = Total Output Capacitance.  
I
C
I
C
Adding slope compensation to the control loop, avoids  
erratic operation of the PWM circuit, particularly at lower  
duty cycles and higher frequencies, where there is not  
enough ramp signal, and provides a more stable switch-  
point.  
Normal Operation  
During Normal operation, Switch Off-Time is constant and  
set by the COFF capacitor. Switch On-Time is adjusted by  
the V2TM Control loop to maintain regulation. This results in  
changes in regulator switching frequency, duty cycle, and  
output ripple in response to changes in load and line.  
Output voltage ripple will be determined by inductor rip-  
ple current and the ESR of the output capacitors  
The scheme that prevents that switching noise prematurely  
triggers the PWM circuit consists of adding a positive volt-  
age slope to the output of the Error Amplifier (COMP pin)  
during an off-time cycle.  
The circuit that implements this function is shown in  
Figure 11.  
14  
Transient Response  
COMP  
The CS51311 V2TM Control Loop’s 200ns reaction time pro-  
vides unprecedented transient response to changes in  
input voltage or output current. Pulse-by-pulse adjustment  
of duty cycle is provided to quickly ramp the inductor cur-  
rent to the required level. Since the inductor current cannot  
be changed instantaneously, regulation is maintained by  
the output capacitor(s) during the time required to slew the  
inductor current.  
C
COMP  
CS51311  
R
C
1
R
1
2
11  
GATE(L)  
To Synchronous FET  
Overall load transient response is further improved  
through a feature called “Adaptive Voltage Positioning”.  
This technique pre-positions the output capacitors voltage  
to reduce total output voltage excursions during changes  
in load.  
Figure 11: Small RC filter provides the proper voltage ramp at the  
beginning of each on-time cycle.  
The ramp waveform is generated through a small RC filter  
that provides the proper voltage ramp at the beginning of  
each on-time cycle. The resistors R1 and R2 in the circuit of  
Figure 11 form a voltage divider from the GATE(L) output,  
superimposing a small artificial ramp on the output of the  
error amplifier. It is important that the series combination  
R1/R2 is high enough in resistance not to load down and  
negatively affect the slew rate on the GATE(L) pin.  
Holding tolerance to 1% allows the error amplifiers refer-  
ence voltage to be targeted +25mV high without compro-  
mising DC accuracy. A “Droop Resistor”, implemented  
through a PC board trace, connects the Error Amps feed-  
back pin (VFB) to the output capacitors and load and carries  
the output current. With no load, there is no DC drop  
across this resistor, producing an output voltage tracking  
the Error amps, including the +25mV offset. When the full  
load current is delivered, a 50mV drop is developed across  
this resistor. This results in output voltage being offset -  
25mV low.  
Protection and Monitoring Features  
Over-Current Protection  
The result of Adaptive Voltage Positioning is that addition-  
al margin is provided for a load transient before reaching  
the output voltage specification limits. When load current  
suddenly increases from its minimum level, the output  
capacitor is pre-positioned +25mV. Conversely, when load  
current suddenly decreases from its maximum level, the  
output capacitor is pre-positioned -25mV. For best  
A loss-less hiccup mode current limit protection feature is  
provided, requiring only the COMP capacitor to imple-  
ment. The CS51311 provides overcurrent protection by  
sensing the current through a “Droop” resistor, using an  
internal current sense comparator. The comparator com-  
pares the voltage drop through the “Droop” resistor to an  
internal reference voltage of 86mV (typical).  
Transient Response, a combination of a number of high fre-  
quency and bulk output capacitors are usually used.  
If the voltage drop across the “Droop” resistor exceeds this  
threshold, the current sense comparator allows the fault  
233