CS5127
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
16 Lead SO Wide
1
SYNC
A pulse train on this lead will synchronize the oscillator. Sync threshold level
is 2.4V. Synchronization frequency should be at least 10% higher than the reg-
ular operating frequency. The sync feature is level sensitive.
The oscillator integrating capacitor is connected to this lead.
The oscillator charge current setting resistor is connected to this lead.
The inverting input of the channel 1 error amplifier is brought out to this lead.
The lead is connected to a resistor divider which provides a measure of the
output voltage. The input is compared to a 1.275V reference, and channel 1
error amp output is used as the V
2
ª PWM control voltage.
Channel 1 error amp output and PWM comparator input.
This lead connects to the non-inverting input of the channel 1 PWM comparator.
This lead is the gate driver for the channel 1 FET. It is capable of providing
nearly 1A of peak current.
This lead provides a ÒquietÓ ground for low power circuitry in the IC. This
lead should be shorted to the PGND lead as close as possible to the IC for best
operating results.
This lead is the power ground. It provides the return path for the FET gate dis-
charge. It should be shorted to the LGND lead as close as possible to the IC for
best operating results.
This lead is the gate driver for the channel 2 FET. See GATE1 lead description
for more details.
This lead connects to the non-inverting input of the channel 2 PWM comparator.
Channel 2 error amp output and PWM comparator input.
Inverting input for the channel 2 error amp. See V
FBI
for more details.
The regulator controlled by channel 2 may be turned on and off selectively by
the user. Pulling the ENABLE lead above 3.5V will turn channel 2 on. Setting
the ENABLE lead voltage below 1.5V guarantees that channel 2 is off.
This lead is the output of a ± 3% reference. This reference drives most of the
on-chip circuitry, but will provide a minimum of 10 mA to external circuitry if
needed. The reference is inherently stable and does not require a compensa-
tion capacitor, but use of a decoupling capacitor will reduce noise in the IC.
This lead is the power supply input to the IC. The maximum input voltage
that can be withstood without damage to the IC is 20V.
2
3
4
C
T
R
T
V
FB1
5
6
7
8
COMP1
V
FFB1
GATE1
LGND
9
PGND
10
11
12
13
14
GATE2
V
FFB2
COMP2
V
FB2
ENABLE
15
V
REF
16
V
IN
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
