CS5124/6
Electrical Characteristics: -40°C
≤
T
J
≤
125°C, -40°C
≤
T
A
≤
105°C, 7.60V
≤
V
CC
≤
20V, UVLO = 3.0V, I
SENSE
= 0V,
C
V(CC)
= 0.33µF, C
GATE
= 1nF (ESR = 10Ω), C
SS
= 470pF C
V(FB)
= 100pF
,
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
Voltage Feedback
V
FB
Pull-up Res.
V
FB
Clamp Voltage
V
FB
Clamp Voltage
V
FB
Fault Voltage Threshold
s
Output Gate Drive
Maximum Sleep
Pull-down Voltage
GATE High (AC)
GATE Low (AC)
GATE High Clamp Voltage
Rise Time
Fall Time
CS5124 Only
CS5126 Only
2.9
2.63
2.40
460
4.3
2.90
2.65
490
8.1
3.15
2.90
520
kΩ
V
V
mV
V
CC
= 6.0V, I
OUT
= 1mA
Series resistance < 1Ω (Note 1)
Series resistance < 1Ω (Note 1)
V
CC
= 20V
Measure GATE rise time,
1V < GATE < 9V; V
CC
=12V
Measure GATE fall time,
9V > GATE > 1V; V
CC
= 12V
V
CC
-1
11.0
1.2
V
CC
-0.5
0.0
13.5
45
25
2.0
V
V
0.5
16.0
65
55
V
V
ns
ns
s
Thermal Shutdown
Thermal Shutdown Temperature (Note 1) (GATE low)
Thermal Enable Temperature
(Note 1) (GATE switching)
Thermal Hysteresis
(Note 1)
Notes
1. Not tested in production. Specification is guaranteed by design.
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
135
100
15
150
125
25
165
150
35
°C
°C
°C
8 Lead SO Narrow
CS5124
1
2
CS5126
1
-
V
CC
BIAS
V
CC
Power Input Pin.
V
CC
Clamp Output Pin. This pin will control the gate of an N-channel MOS-
FET that in turn regulates V
CC
. This pin is internally clamped at 15V when
the IC is in sleep mode.
Clock Synchronization Pin. A positive edge will terminate the current PWM
cycle. Ground this pin when it is not used.
Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the
chip to "wake up" however the GATE remains low. A voltage greater than
2.6V on this pin allows the output to switch.
Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is
charged with 10µA and discharged with 10mA. The Soft Start capacitor con-
trols both soft-start time and hiccup mode frequency.
Voltage Feedback Pin. The collector of an optocoupler is typically tied to this
pin. This pin is pulled up internally by a 4.3kΩ resistor to 5V and is clamped
internally at 2.9V(2.65V). If V
FB
is pulled > 4V, the oscillator is disabled and
GATE will stay high. If the V
FB
pin is pulled < 0.49V, GATE will stay low.
Current Sense Pin. This pin is connected to the current sense resistor on the
primary side. If V
FB
is floating, the GATE will go low if I
SENSE
= 195mV
(335mV). If I
SENSE
> 275mV (525mV), Soft Start will be initiated.
Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally
clamped to 13.5V.
Ground Pin.
4
-
3
3
2
SYNC
UVLO
4
4
SS
5
5
V
FB
6
6
I
SENSE
7
8
7
8
GATE
Gnd
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
