CS5124/6
Electrical Characteristics: -40°C
≤
T
J
≤
125°C, -40°C
≤
T
A
≤
105°C, 7.60V
≤
V
CC
≤
20V, UVLO = 3.0V, I
SENSE
= 0V,
C
V(CC)
= 0.33µF, C
GATE
= 1nF (ESR = 10Ω), C
SS
= 470pF C
V(FB)
= 100pF
,
unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
s
V
CC
Clamp and BIAS Pin
V
CC
Clamp Voltage
BIAS Minimum Voltage
BIAS Clamp
s
200kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
CS5124 Only. Connect an NFET as follows: BIAS = G, V
CC
= S, V
IN
= D.
36V
≤
V
IN
≤
60V, 220nF
≤
C
SS
≤
500nF, R = 500k
Measure Voltage on BIAS with:
10V
≤
V
CC
≤
20V and 50µA
≤
I
BIAS
≤
1mA
With BIAS pin sinking 1mA
CS5126 Only
175
78
12
200
82.5
18
225
85
23
kHz
%
mV/µs
7.275
1.6
12
7.9
2.8
15
8.625
4
20
V
V
V
Slope Compensation
(Normal operation)
Slope Compensation
(Synchronized operation)
(Note 1)
SYNC Input Threshold Voltage
SYNC Input Impedance
Measured with SYNC = 1V &10V
s
400kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
Slope Compensation
s
Soft Start
Soft Start Charge Current
Soft Start Discharge Current
V
SS
Voltage when V
FB
Begins to Rise
V
FB
= 300mV
CS5124 Only
7
1
50
12
2
120
16
3
230
mV/µs
V
kΩ
360
80.0
15
400
82.5
21
440
85.0
26
kHz
%
mV/µs
7
0.5
1.40
4.7
200
10
10.0
1.62
4.9
275
13
1.80
µA
mA
V
V
mV
Peak Soft Start Charge Voltage
Valley Soft Start Discharge Voltage
s
Current Sense
CS5124 Only
First Current Sense Threshold
At max duty cycle.
Second Current Sense Threshold
I
SENSE
to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
s
Current Sense
First Current Sense Threshold
Second Current Sense
Threshold
I
SENSE
to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
0 to 700mV pulse into I
SENSE
(after blanking time)
0 to 400mV pulse into I
SENSE
(Note 1)
CS5126 Only
At max duty cycle
400
170
250
60
90
195
275
90
130
60
215
315
130
180
mV
mV
ns
ns
mV
300
485
60
110
335
525
90
175
125
360
575
130
210
mV
mV
ns
ns
mV
0 to 800mV pulse into I
SENSE
(after blanking time)
0 to 550mV pulse into I
SENSE
(Note 1)
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
