CS5112
Circuit Description: continued
If a correct watchdog signal is not received within the
specified time a reset pulse train is issued until the correct
watchdog signal is received. The nominal reset signal in
this case is a 5 volt square wave with a 50% duty cycle as
shown in Figure 4.
The RESET signal frequency is given by:
1
f
RESET
=
2(t
WDI
)
The Power On Reset (POR) and low voltage RESET use
the same circuitry and issue a reset when the linear output
voltage is below the regulation limit. After V
LIN
rises
above the minimum specified value, RESET remains low
for a fixed period t
POR
as shown in Figure 5.
The POR delay (t
POR
) is given by:
t
POR
= 1.353
´
C
Delay
R
BIAS
V
LIN
4.45V
4.25V
RESET
The switching regulator begins operation when V
REG
and
V
IN
are raised above 5 volts. V
REG
is required since the
switching supplyÕs control circuitry is powered through
V
LIN
. V
IN
supplies the base drive to the switcher output
transistor.
The output transistor turns on when the oscillator starts to
charge the capacitor on C
OSC
. The output current will
develop a voltage drop across the internal sense resistor
(R
S
). This voltage drop produces a proportional voltage at
the output of the current sense amplifier, which is com-
pared to the output of the error amplifier. The error ampli-
fier generates an output voltage which is proportional to
the difference between the scaled down output boost volt-
age (V
FB1
or V
FB2)
and the internal bandgap voltage refer-
ence. Once the current sense amplifier output exceeds the
error amplifierÕs output voltage, the output transistor is
turned off.
The energy stored in the inductor during the output tran-
sistor on time is transferred to the load when the output
transistor is turned off. The output transistor is turned
back on at the next rising edge of the oscillator. On a cycle
by cycle basis, the current mode controller in a discontinu-
ous mode of operation charges the inductor to the appro-
priate amount of energy, based on the energy demand of
the load. Figure 7 shows the typical current and voltage
waveforms for a boost supply operating in the discontinu-
ous mode.
NOTES:
V
RLO
V
RPEAK
t
POR
Figure 5a. The power on reset time interval (t
POR
) begins when V
LIN
rises above 4.45V (typical).
V
LIN
5V
4.25V
1. Refer to Figure 1d to determine oscillator frequency.
2. The switching regulator can be disabled by providing a
logic high at the ENABLE input.
3. The boost output voltage can be controlled dynamically
by the feedback select input. If select is open, V
FB2
is
selected. If select is low, then V
FB1
is selected.
Protection Circuitry
RESET
5V
The current out of V
LIN
is sensed in order to limit exces-
sive power dissipation in the linear output transistor over
the output range of 0V to regulation. Also, the current into
V
SW
is sensed in order to provide the current limit func-
tion in the switcher output transistor.
If the die temperature is increased above 160¡C, either due
to excessive ambient temperature or excessive power dis-
sipation, the drive to the linear output transistor is
reduced proportionally with increasing die temperature.
Therefore, V
LIN
will decrease with increasing die tempera-
ture above 160¡C. Since the switcher control circuitry is
powered through V
LIN
, the switcher performance, includ-
ing current limit, will be affected by the decrease in V
LIN
.
t
POR
Figure 5b. RESET signal is issued whenever V
LIN
falls below 4.25V
(typical).
Current Mode PWM Switching Circuitry
The current mode PWM switching voltage regulator con-
tains an error amplifier with selectable feedback inputs, a
current sense amplifier, an adjustable oscillator and a 1.4A
output power switch with antisaturation control. The
switching regulator and external components, connected
in a boost configuration, are shown in Figure 6.
6
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
