CS5112
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
FUNCTION
24 Lead SO Wide
1
2, 3
4
5,6,7,8,17,18,19,20
9
10
11
12
13
14
15
16
21
22
23
24
V
IN
NC
V
SW
Gnd
V
FB1
V
FB2
SELECT
COMP
C
OSC
WDI
C
Delay
RESET
I
BIAS
V
LIN
V
REG
ENABLE
Supply Voltage.
No connection.
Collector of NPN power switch for switching regulator section.
Connected to the heat removing leads.
Feedback input voltage 1 (referenced to 1.25V)
Feedback input voltage 2 (referenced to 1.25V)
Logic level input that selects either V
FB1
or V
FB2
. An open selects
V
FB2
. Connect to Gnd to select V
FB1
.
Output of the transconductance error amplifier.
A capacitor connected to Gnd sets the switching frequency.
Refer to Figure 1d.
Watchdog input. Active on falling edge.
A capacitor connected to Gnd sets the Power On Reset and
Watchdog time.
RESET output. Active low if V
LIN
is below the regulation limit.
If watchdog timeout is reached, a reset pulse train is issued.
A resistor connected to Gnd sets internal bias currents as well as
the C
OSC
and C
Delay
charge currents.
Regulated 5V output from the linear regulator section.
Input voltage to the linear regulator and the internal supply cir-
cuitry.
Logic level input to shut down the switching regulator.
Typical Performance Characteristics
4.5mA
0A
-10mA
I
REG
- I
LIN
I
IN
20mA
40mA
60mA
80mA
100mA
4.0mA
-20mA
-30mA
3.5mA
0A
-40mA
0A
0.5A
1.0A
1.5A
2.0A
I
LIN
I
SW
Figure 1a. 5V Regulator Bias Current vs. Load Current.
1.4V
1.2V
1.0V
Figure 1b. Supply Current vs. Switch Current.
180
160
Frequency (kHz)
140
120
100
80
60
40
20
V
SW
0.8V
0.6V
0.4V
0.2V
0.0V
0A
0.5A
1.0A
1.5A
2.0A
0
0
500
1000
1500
2000
2500
3000
ISW
C
OSC
(pF)
Figure 1c. Switch Saturation Voltage.
Figure 1d. Oscillator Frequency (kHz) vs. C
OSC
(pF), assuming R
BIAS
=
64.9k�½.
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
