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CS5106LSWR24 参数 Datasheet PDF下载

CS5106LSWR24图片预览
型号: CS5106LSWR24
PDF下载: 下载PDF文件 查看货源
内容描述: 多重功能,同步加辅助PWM控制器 [Multi-Feature, Synchronous plus Auxiliary PWM Controller]
分类和应用: 控制器
文件页数/大小: 12 页 / 199 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Theory of Application: continued  
age comparator has its positive input referenced to 5V  
7.5V  
while the over voltage comparator has its negative input  
referenced to 5V. The output of both comparators are  
ORed at (G4) with the over current and enable inputs. The  
output of G4 feeds the input to the fault latch (F2).  
V
CC  
V
,V  
,RUN1  
REF REF(OK)  
CLK1  
GATE1  
PROGRAM and ENABLE Leads  
V
FB1  
The PROGRAM lead controls the polarity of the ENABLE  
lead. If the PROGRAM lead is ÔhighÕ or floating, the GATE  
outputs will go low if the ENABLE input is tied ÔhighÕ or  
floating. If the PROGRAM lead is tied low, the GATE out-  
puts will go low if the ENABLE input is tied ÔlowÕ. If the  
part is then enabled after switching the outputs low, the  
part will restart according to the procedure outlined in the  
ÒStartupÓ section.  
RAMP1  
V
SS  
> V  
CC  
V
SS  
RUN2  
CLK2  
GATE2  
GATE2B  
FAULT Logic  
V
FB2  
If a VREF, UVSD or OVSD fault occurs at any time, G4  
resets the fault latch (F2). RUN1 goes low and all gate  
drivers cease switching and return to their ÔlowÕ state.  
When RUN1 goes low, the output of the auxiliary op-amp  
(A1) discharges the soft start capacitor and holds it low  
while RUN1 is low. If the fault condition is removed before  
the OUVDELAY timer is tripped, the IC will restart the  
power supplies when VSS < 1.4V. If the OUVDELAY timer  
trips, the power supply must be restarted as explained in  
the following section.  
RAMP2  
Figure 1: Startup waveforms.  
Voltage and Current Ramp PWM Comparator Inputs  
(VFB1,2 and RAMP1,2 leads)  
C10 and C11 are the PWM comparators for the auxiliary  
and main supplies. The feedback voltage (VFB) is divided  
by three and compared with a linear, voltage representa-  
tion of the current in the primary side of the transformer  
(RAMP). When the output of the feedback comparator  
goes ÔhighÕ, a reset signal is sent to the PWM flip-flop and  
the GATE driver is driven ÔlowÕ. A 130mV offset on the  
RAMP leads allows the drivers to go to 0% duty cycle in  
the presence of light loads.  
Output Undervoltage Delay Timer for the Main and  
Auxiliary Regulated Outputs  
C7 and C4 are the output under voltage monitor compara-  
tors for the auxiliary and main supplies. If a regulated out-  
put drops such that its associated VFB voltage exceeds 4.1V,  
the output undervoltage monitor comparator goes ÔhighÕ  
and the OUVDELAY capacitor begins charging from 0V. A  
timing relation is set up by a 10µA nominal current source,  
the OUVDELAY capacitor and a 5V fault threshold at the  
input of C2 (see Figure 2). If any regulated output drops  
and stays low for the entire charge time of the OUVDELAY  
capacitor, a fault is triggered and all GATE drivers will go  
into a low state.  
Feedback Voltage for GATE1 Driver (VFB1  
)
Typically the output of the auxiliary error amplifier (A1) is  
tied to VFB1. The VSS output is programmed to 12V by a  
10:1 resistive divider on the negative input of the error  
amplifier and a fixed 1.2V reference on the positive input  
of the error amplifier.  
Pulse by Pulse Over Current Protection and Hiccup  
Mode (ILIM1,2 leads)  
Once this fault is triggered, the IC will restart the power  
supplies only if the OUVDELAY fault is reset and ENABLE  
or UVSD is toggled while VSS < 1.4V. To reset the OUVDE-  
LAY fault, both the VFB inputs must be less than 4.1V. In  
the application circuit shown, VFB1 is brought low by  
OAOUT when RUN1 stops the oscillators. VFB2 is brought  
low when VAUXP bleeds down and the VFB2 opto-isolator is  
no longer powered.  
C12 and C13 are the pulse by pulse current limit compara-  
tors for the auxiliary and main supplies. When the current  
in the primary side of the transformer increases such that  
the voltage across the current sense resistor exceeds 1.2V  
nominal, the output of the current limit comparator goes  
ÔhighÕ and a reset signal is sent to the PWM flip-flop and  
the GATE driver is driven ÔlowÕ.  
C16 and C17 are the second threshold, pulse by pulse cur-  
rent limit comparators for the auxiliary and main supplies.  
If the current in the primary side of the transformer  
increases so quickly that the current sense voltage is not  
limited by C12 or C13 and the voltage across the current  
sense resistor exceeds 1.4V, the second threshold compara-  
tor will trip a delay circuit and force the GATE driver stage  
to go low and stay low for the next two clock cycles.  
1000  
100  
10  
1
Undervoltage and Overvoltage Thresholds  
C5 and C8 are the undervoltage and overvoltage detection  
comparators. Typically, these inputs are tied across the  
middle resistor in a three resistor divider with the top  
resistor to VIN and bottom resistor to Ground. The under  
voltage comparator has 200mV of built in hysteresis with  
respect to a direct input on the UVSD lead. The under volt-  
0.1  
0.01  
0.1  
1
10  
100  
1000  
CAPACITANCE (nF)  
Figure 2: OUVDELAY Time vs. OUVDELAY Capacitance  
9