CM6500UN (1MHz PFC)
http://www.championmicro.com.tw
EPA/90+ ZVS-Like PFC CONTROLLER
Design for High Efficient Power Supply at both Full Load and Light Load
Generating VCC
A filter network is recommended between VCC (pin 11) and
After turning on CM6500UN at 11V, the operating voltage
can vary from 10V to 21V. That’s the two ways to generate
VCC. One way is to use auxiliary power supply around 15V,
and the other way is to use bootstrap winding to self-bias
CM6500UN system. The bootstrap winding can be either
taped from PFC boost choke or from the transformer of the
DC to DC stage. The ratio of winding transformer for the
bootstrap should be set between 18V and 15V.
bootstrap winding. The resistor of the filter can be set as
following.
RFILTER x IVCC ~ 2V, IVCC = IOP + (QPFCFET + QPWMFET ) x fsw
IOP = 2.1mA (typ.)
If anything goes wrong, and VCC goes beyond 19.4V, the
PFC gate (pin 10) drive goes low remains function. The
resistor’s value must be chosen to meet the operating current
requirement of the CM6500UN itself (5mA, max.) plus the
current required by the two gate driver outputs.
EXAMPLE:
With a wanting voltage called, VBIAS ,of 18V, a VCC of 15V
and the CM6500UN driving a total gate charge of 90nC at
100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET),
the gate driver current required is:
IGATEDRIVE = 100kHz x 90nC = 9mA
V
BIAS − VCC
RBIAS
RBIAS
=
=
I
CC + I
G
18V −15V
5mA + 9mA
Choose RBIAS = 214Ω
In case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during OFF time of the switch.
The CM6500UN should be locally bypassed with a 1.0 μF
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47 μ F and 220 μ F is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
Figure 5 shows a leading edge control scheme.
One of the advantages of this control technique is that it
required only one system clock. Switch 1(SW1) turns off and
switch 2 (SW2) turns on at the same instant to minimize the
momentary “no-load” period, thus lowering ripple voltage
generated by the switching action. With such synchronized
switching, the ripple voltage of the first stage is reduced.
Calculation and evaluation have shown that the 120Hz
component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
on right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp
up. The effective duty cycle of the trailing edge modulation is
determined during the ON time of the switch. Figure 4 shows
a typical trailing edge control scheme.
2014/11/11 Rev. 1.0
Champion Microelectronic Corporation
16
CHAMP [ CHAMPION MICROELECTRONIC CORP. ]
