24LLC16
16K-Bit-Serial EEPROM
tF
tHIGH
tR
tLOW
SCL
SDA In
tSU:STA
tHD:STA tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
SDA Out
Figure 5-15. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
ACK
WORDn
WR
t
Stop
Condition
Start
Condition
Figure 5-16. Write Cycle Timing Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Email: server@ceramate.com.tw
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Rev 1.0 Aug.5, 2002
Page 16 of 22
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