24LLC16
16K-Bit-Serial EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the 24LLC16 This method of write protection is
controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The 24LLC16 will acknowledge slave and word address, but it will not generate an acknowledge after
receiving first byte of data. In this situation the write cycle will not be started when a stop condition is generated.
By connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to protect data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
The WP pin is internally pulled down to VSS.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the 24LLC16 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends eight bits
of data. In a current address byte read operation the master does not acknowledge the data, and it generates a
Stop condition, forcing the 24LLC16 to stop the transmission (see Figure 5-12).
Start
Slave Address
Data
Stop
A
C
K
N
O
A
C
K
Figure 5-12. Current Address Byte Read Operation
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.5, 2002
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