CAT93C86
PIN CAPACITANCE
Symbol
Test
Conditions
VOUT=0V
VIN=0V
Min
Typ
Max
Units
pF
(1)
COUT
Output Capacitance (DO)
5
5
(1)
CIN
Input Capacitance (CS, SK, DI, ORG)
pF
INSTRUCTION SET
Start
Address
Data
Instruction
Bit
Opcode
10
x8
x16
x8
x16
Comments
READ
1
A10-A0
A10-A0
A10-A0
A9-A0
A9-A0
A9-A0
Read Address AN– A0
Clear Address AN– A0
ERASE
WRITE
EWEN
EWDS
ERAL
1
11
1
01
D7-D0 D15-D0 Write Address AN– A0
Write Enable
1
00
11XXXXXXXXX 11XXXXXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXXXXXX 10XXXXXXXX
01XXXXXXXXX 01XXXXXXXX
1
00
Write Disable
1
00
Clear All Addresses
WRAL
1
00
D7-D0 D15-D0 Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC
=
VCC
=
VCC
=
1.8V-6V
2.5V-6V
4.5V-5.5V
Test
Symbol Parameter
Conditions
Min Max Min
Max Min
Max
Units
ns
tCSS
tCSH
tDIS
CS Setup Time
200
0
100
0
50
0
CS Hold Time
ns
DI Setup Time
200
200
100
100
50
50
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
1
1
0.5
0.5
200
5
0.15
0.15
100
5
µs
CL = 100pF
(3)
Output Delay to 0
µs
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
5
ns
tEW
ms
µs
tCSMIN
tSKHI
tSKLOW
tSV
1
1
1
0.5
0.5
0.5
0.15
0.15
0.15
µs
µs
1
0.5
0.1
µs
SKMAX
DC
500
DC
1000 DC
3000
kHz
Doc. No. 1091, Rev. M
3
CATALYST [ CATALYST SEMICONDUCTOR ]
