93C46/56/57/66/86
Erase All
Upon receiving an ERAL command, the CS (Chip Se-
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking
clear cycle of the selected memory location. The clock-
ing of the SK pin is not necessary after the device has
enteredtheselfclockingmode.Theready/busystatusof
the CAT93C46/56/57/66/86 can be determined by se-
lecting the device and polling the DO pin. Once cleared,
the content of a cleared location returns to a logical “1”
state.
lect) pin must be deselected for a minimum of tCSMIN
.
The falling edge of CS will start the self clocking clear
cycle of all memory locations in the device. The clocking
of the SK pin is not necessary after the device has
enteredtheselfclockingmode.Theready/busystatusof
the CAT93C46/56/57/66/86 can be determined by se-
lecting the device and polling the DO pin. Once cleared,
the contents of all memory bits return to a logical “1”
state.
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
The CAT93C46/56/57/66/86 powers up in the write
disable state. Any writing after power-up or after an
EWDS (write disable) instruction must first be preceded
by the EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C46/56/57/66/86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
statusoftheCAT93C46/56/57/66/86canbedetermined
by selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Figure 4. Erase Instruction Timing
SK
CS
STANDBY
STATUS VERIFY
t
CS
A
N
A
0
A
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
93C46/56/57/66/86 F06
Doc. No. 25056-00 2/98 M-1
7
CATALYST [ CATALYST SEMICONDUCTOR ]
