CAT24C164
Figure 9. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
N
O
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
S
S
P
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
Figure 11. Sequential Read Sequence
N
O
BUS ACTIVITY:
SLAVE
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
MASTER
ADDRESS
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1118, Rev. A
9