CAT24C164
Figure 1. START/STOP Conditions
SCL
SDA
START
STOP
CONDITION
CONDITION
Figure 2. Slave Address Bits
1
A2
A1
A0
a
a
a
8
R/W
CAT24C164
10
9
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
t
BUF
t
t
AA
DH
SDA OUT
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1118, Rev. A
5