CAT24C128
Figure 9. Immediate Read Sequence and Timing
N
O
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
C
K
DATA
BYTE
SLAVE
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
A
R
T
N
O
A
C
K
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
a
–a
a –a
13
8
7
0
S
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
SLAVE
= Don't Care Bit
*
Figure 11. Sequential Read Sequence
BUS ACTIVITY:
SLAVE
N
O
S
A T
C O
K P
MASTER
ADDRESS
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
SLAVE
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
9