CAT24C128
Figure 5. Byte Write Sequence
BUS ACTIVITY:
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE
S
T
O
P
DATA
BYTE
SLAVE
ADDRESS
MASTER
a
–a
a –a
13
8
7
0
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
= Don't Care Bit
*
Figure 6. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
ADDRESS
BYTE
–a
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
SLAVE
ADDRESS
a
a –a
13
8
7 0
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
= Don't Care Bit
P ≤ 63
*
Figure 8. WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
a
a
d
7
d
0
SDA
WP
7
0
t
SU:WP
t
HD:WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-1103, Rev. J
7
CATALYST [ CATALYST SEMICONDUCTOR ]
