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CAT1021WI-25T2 参数 Datasheet PDF下载

CAT1021WI-25T2图片预览
型号: CAT1021WI-25T2
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行2K位CMOS EEPROM ,手动复位及看门狗定时器 [Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer]
分类和应用: 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 21 页 / 278 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1021, CAT1022, CAT1023  
Immediate/Current Address Read  
Sequential Read  
The CAT1021/22/23 address counter contains the  
address of the last byte accessed, incremented by  
one. In other words, if the last READ or WRITE  
access was to address N, the READ immediately  
following would access data from address N + 1. For  
N = E = 255, the counter will wrap around to zero  
and continue to clock out valid data. After the  
CAT1021/22/23 receives its slave address infor-  
The Sequential READ operation can be initiated by  
either the Immediate Address READ or Selective READ  
operations. After the CAT1021/22/23 sends the inital 8-  
bit byte requested, the Master will responds with an  
acknowledge which tells the device it requires more  
data. The CAT1021/22/23 will continue to output an 8-  
bit byte for each acknowledge, thus sending the STOP  
condition.  
¯¯  
mation (with the R/W bit set to one), it issues an  
The data being transmitted from the CAT1021/22/23 is  
sent sequentially with the data from address N followed  
by data from address N + 1. The READ operation  
address counter increments all of the CAT1021/22/23  
address bits so that the entire memory array can be  
read during one operation.  
acknowledge, then transmits the 8-bit byte  
requested. The master device does not send an  
acknowledge, but will generate a STOP condition.  
Selective/Random Read  
Selective/Random READ operations allow the  
Master device to select at random any memory  
location for a READ operation. The Master device  
first performs a ‘dummy’ write operation by sending  
the START condition, slave address and byte  
addresses of the location it wishes to read. After the  
CAT1021/22/23 acknowledges, the Master device  
sends the START condition and the slave address  
¯¯  
again, this time with the R/W bit set to one. The  
CAT1021/22/23 then responds with its acknowledge  
and sends the 8-bit byte requested. The master  
device does not send an acknowledge but will  
generate a STOP condition.  
Figure 11. Selective Read Timing  
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
SLAVE  
ADDRESS  
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n  
A
C
K
Figure 12. Sequential Read Timing  
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
SDA LINE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
13  
Doc. No. 3009 Rev. L  
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