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CSPPT32-101J 参数 Datasheet PDF下载

CSPPT32-101J图片预览
型号: CSPPT32-101J
PDF下载: 下载PDF文件 查看货源
内容描述: 芯片级并行终端阵列 [CHIP SCALE PARALLEL TERMINATION ARRAY]
分类和应用:
文件页数/大小: 4 页 / 61 K
品牌: CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
 浏览型号CSPPT32-101J的Datasheet PDF文件第2页浏览型号CSPPT32-101J的Datasheet PDF文件第3页浏览型号CSPPT32-101J的Datasheet PDF文件第4页  
CALIFORNIA MICRO DEVICES  
CSPPT  
Chip Scale ParallelTermination Array  
Features  
Applications  
• 8,16 or 32 integrated high frequency  
bussed terminations  
• Parallel resistive bus termination  
• Bussed resistor array  
• Ultra small footprint Chip Scale Package  
• Ceramic substrate  
• 0.35mm Eutectic Solder Bumps, 0.65mm pitch  
Product Description  
The CSPPT is a high performance Integrated Passive  
Device (IPD) which provides parallel terminations  
suitable for use in high speed bus applications. Eight (8),  
sixteen (16), or thirty-two (32) parallel termination  
versions are provided. These resistors provide excellent  
high frequency performance in excess of 3GHz and are  
manufactured to an absolute tolerance as low as 1ꢀ.  
The Chip Scale Package provides an ultra small  
footprint for this IPD and provides minimal parasitics  
compared to conventional packaging. Typical bump  
inductance is less than 25pH. The large solder bumps  
and ceramic substrate allow for standard attachment to  
laminate printed circuit boards without the use of  
underfill.  
SCHEMATIC DIAGRAMS  
B
A
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
1
2
3
4
5
CSPPT08  
D
D
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
C
B
C
B
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
R1  
A
A
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10  
CSPPT16  
CSPPT32  
© 2000 California Micro Devices Corp. All rights reserved.  
C1290700  
11/10/2000 215 Topaz Street, Milpitas, California 95035  
Tel: (408) 263-3214  
Fax: (408) 263-7846  
www.calmicro.com  
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