PRELIMINARY
CM2031
Specifications (cont’d)
(SEE NOTE 1)
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ICC5
Operating Supply Current
5V_SUPPLY = 5.0V, CEC_OUT =
3.3V, LV_SUPPLY= CE_SUPPLY=
3.3V, DDC=5V; Note 7
300
μA
ICCLV
ICCCE
Bias Supply Current
Bias Supply Current
LV_SUPPLY = 3.3V; Note 7
10
μA
μA
CE_SUPPLY = 3.3V,
CEC_OUT=0V; Note 7
130
IOFF
OFF state leakage current,
level shifting NFET
0.1
0.1
5
μA
μA
LV_SUPPLY = 0V
IBACKDRIVE
Current conducted from output 5V_SUPPLY < VCH_OUT; Signal
pins to V_SUPPLY rails when
powered down
pins: TMDS_[2:0]+/-, TMDS_CK+/-,
CE_REMOTE_OUT,
DDC_DAT_OUT, DDC_CLK_OUT,
HOTPLUG_DET_OUT, 5V_OUT
Only
CECSL
CECRT
CEC Slew Limit
CEC Rise Time
Measured from10-90% or 90-10%
0.02
V/μs
μs
Measured from 10-90%
Assumes a signal swing from 0-3.3V
26.4
26.4
0.8
250
50
CECFT
RHOTPLUG
VTH
CEC Fall Time
Measured from 90-10%
Assumes a signal swing from 0-3.3V
μs
kΩ
V
Hotplug Resistance
Voltage on HotPlug_In is greater
than the specified range below
1
1.2
5.5
Threshold Voltage to Assert
1.5
1kΩ
Turn On Threshold of I2C/
DDC Accelerator
VACC
Voltage is 0.3*5V_Supply
1.5
0.4
V
I2C/DDC Output Level when
Logic Low Applied Locally
(ASIC side)
VOL(DDC_OUT)
4mA Sink on DDC_IN,
LV_SUPPLY=3.3V, 1.5kΩ pullup on
DDC_OUT to 5.0V, Note 2
0.8
0.8
0.4
1
V
V
VOL(DDC_IN) Logic Level (ASIC side) when DDC_OUT=1.2V,
0.4
0.3
I2C/DDC Logic Low Applied;
LV_SUPPLY=3.3V, 1.5kΩ pullup on
DDC_OUT to 5.0V, Note 2
2
( I C-CMOS compatibility)
VOL(DDC_IN) Logic Level (ASIC side) when DDC_OUT=0.4V,
V
I2C/DDC Logic Low Applied;
LV_SUPPLY=3.3V, 1.5kΩ pullup on
DDC_OUT to 5.0V, Note 2
2
( I C pass-through compatibility)
tr(DDC)
DDC_OUT Line Risetime,
DDC_IN floating,
μs
VACC < VDDC_OUT
<
LV_SUPPLY=3.3V, 1.5kΩ pullup on
DDC_OUT to 5.0V, Bus Capacitance
= 4000pF, Note 2
(5V_Supply-0.5V)
VF
Diode Forward Voltage
Top Diode
IF = 8mA, TA = 25°C, Note 2
0.6
0.6
0.85
0.85
0.95
0.95
V
V
Bottom Diode
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8/8/2006 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
✍
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✍
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9
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