PRELIMINARY
CM2031
PACKAGE / PINOUT DIAGRAM
TOP VIEW
1
38
37
36
5V_SUPPLY
N/C
2
CE_SUPPLY
GND
LV_SUPPLY
GND
3
4
TMDS_D2+
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
TMDS_D2+
TMDS_GND
TMDS_D2•
5
TMDS_GND
TMDS_D2•
6
7
TMDS_D1+
TMDS_D1+
TMDS_GND
TMDS_D1•
8
TMDS_GND
TMDS_D1•
9
10
11
12
TMDS_D0+
TMDS_D0+
TMDS_GND
TMDS_D0•
TMDS_GND
TMDS_D0•
TMDS_CK+
TMDS_GND
TMDS_CK•
13
TMDS_CK+
TMDS_GND
TMDS_CK•
14
15
16
17
18
19
CE_REMOTE_IN
DDC_CLK_IN
DDC_DAT_IN
HOTPLUG_DET_IN
CE_REMOTE_OUT
DDC_CLK_OUT
DDC_DAT_OUT
HOTPLUG_DET_OUT
38-PIN TSSOP PACKAGE
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PINS
NAME
ESD Level
DESCRIPTION
8kV3
8kV3
8kV3
8kV3
8kV3
8kV3
8kV3
8kV3
2kV4
8kV3
2kV4
8kV3
2kV4
8kV3
2kV4
8kV3
TMDS 0.9pF ESD protection1.
TMDS 0.9pF ESD protection1.
TMDS 0.9pF ESD protection1.
TMDS 0.9pF ESD protection1.
TMDS 0.9pF ESD protection1.
TMDS 0.9pF ESD protection1.
TMDS 0.9pF ESD protection1.
4, 35
TMDS_D2+
6, 33
7, 32
9, 30
10, 29
12, 27
13, 26
15, 24
16
TMDS_D2•
TMDS_D1+
TMDS_D1•
TMDS_D0+
TMDS_D0•
TMDS_CK+
TMDS 0.9pF ESD protection1.
TMDS_CK•
CE_REMOTE_IN
CE_REMOTE_OUT
DDC_CLK_IN
DDC_CLK_OUT
DDC_DAT_IN
DDC_DAT_OUT
HOTPLUG_DET_IN
HOTPLUG_DET_OUT
CE_SUPPLY referenced logic level in.
23
5V_SUPPLY referenced logic level out plus 10pF ESD.
LV_SUPPLY referenced logic level in.
17
22
5V_SUPPLY referenced logic level out plus 10pF ESD.
LV_SUPPLY referenced logic level in.
18
21
5V_SUPPLY referenced logic level out plus 10pF ESD.
LV_SUPPLY referenced logic level in.
19
20
5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1μF
bypass ceramic capacitor is recommended on this pin2.
Bias for CE / DDC / HOTPLUG level shifters.
2kV4
2kV4,2
2kV4
2
37
1
LV_SUPPLY
CE_SUPPLY
5V_SUPPLY
CEC bias voltage. Previously CM2020 ESD_BYP pin.
Current source for 5V_OUT, VREF for DDC I2C voltage references,
and bias for 8kV ESD pins.
38
N/C
N/A
N/C
© 2005, 2006 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
✍
Tel: 408.263.3214
✍
Fax: 408.263.7846
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www.calmicro.com
8/8/2006