CM1223
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 6, which illus-
trates an example of a positive 8kV ESD pulse striking
an input channel. The 8kV ESD current pulse will divert
along the path as indicated in Figure 4, through the D1
diode and the Zener diode back to the ground rail.
The CM1223 has an integrated backdrive diode
between V and V to prevent backdrive current flow
P
N
from the powered sources.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges.
Additional Information
See also California Micro Devices Application Note
AP209, “Design Considerations for ESD Protection”, in
the Applications section at www.cmd.com.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. The CM1223 has a fast response time of
less than 1ns and low clamp voltage to handle this
pulse.
Similarly for negative ESD pulses, parasitic series
inductance from the V pin to the ground rail will lead
N
to drastically increased negative voltage on the line
being protected.
VCC
POSITIVE SUPPLY
VP
One Channel of
CM1223
LINE BEING PROTECTED
30A
PATH OF POSI-
TIVE ESD CUR-
RENT PULSE I
ESD
D1
0A
SYSTEM OR
CIRCUITRY
BEING
8kV ESD Pulse
I/O pin
D2
PATH OF NEGATIVE
ESD
VN
GROUND RAIL
CHASSIS GROUND
Figure 6. Application of Positive ESD Pulse between Input Channel and Ground
© 2006 California Micro Devices Corp. All rights reserved.
08/02/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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Tel: 408.263.3214
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Fax: 408.263.7846
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9
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
