CM1209
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to
Figure 4,
which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L
1
and L
2
. The volt-
age V
CL
on the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
)
/
dt
+ L
2
x d(I
ESD
)
/
dt
The CM1209 has an integrated Zener diode between
V
P
and V
N
. This greatly reduces the effect of supply rail
inductance L
2
on V
CL
by clamping V
P
at the breakdown
voltage of the Zener diode. However, for the lowest
possible V
CL
, especially when V
P
is biased at a voltage
significantly below the Zener breakdown voltage, it is
recommended that a 0.22µF ceramic chip capacitor be
connected between V
P
and the ground plane.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
P
pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
where I
ESD
is the ESD current pulse, and V
SUPPLY
is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
ESD
)/dt can be approximated by
∆I
ESD
/∆t, or 30/(1x10
-9
). So just 10nH of series induc-
tance (L
1
and L
2
combined) will lead to a 300V incre-
ment in V
CL
!
Similarly for negative ESD pulses, parasitic series
inductance from the V
N
pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Additional Information
See California Micro Devices Application Note AP209,
“Design Considerations for ESD Protection", under
Applications at www.calmicro.com.
L
2
V
P
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE I
ESD
0.22µF
D
1
ONE
CHANNEL
D
2
OF
CM1209
L
1
CHANNEL
INPUT
20A
LINE BEING
PROTECTED
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
V
CL
GROUND RAIL
0A
V
N
CHASSIS GROUND
Figure 4. Application of Positive ESD Pulse between Input Channel and Ground
© 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
01/09/04
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
