PRODUCT SPECIFICATION
TMC2490A
Control Registers
The TMC2490A is initialized and controlled by a set of reg-
isters which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D
7-0
, is governed by
pins CS, R/W, and ADR. The serial port is controlled by
SDA and SCL.
Table 1. Control Register Map
Reg
00
01
02
03
04
04
04
04
04
04
04
05
05
05
05
05
05
05
05
06
06
06
07-
0D
Bit
7-0
7-0
7-0
7-0
7
6
5
4
3
2
1-0
7
6
5
4
3
2
1
0
7-6
5-3
2-0
7-0
Mnemonic
PARTID2
PARTID1
PARTID0
REVID
MASTER
NGSEL
YCDELAY
RAMPEN
YCDIS
COMPDIS
FORMAT
PALN
BURSTF
CHRBW
SYNCDIS
BURDIS
LUMDIS
CHRDIS
PEDEN
Reserved
FIELD
Reserved
Reserved
Function
Reads back 97h
Reads back 24h
Reads back 90h (91h)
Silicon revision #
Master Mode
NTSC Gain Select
Luma to chroma delay
Modulated ramp enable
LUMA, CHROMA disable
COMPOSITE disable
Television standard select
Select PAL-N Subcarrier
Burst flag disable
Chroma bandwidth select
Sync pulse disable
Color burst disable
Luminance disable
Chrominance disable
Pedestal enable
Program LOW
Field ID (Read only)
Program LOW
Program LOW
20
21
22
22
22
22
22
10-
1F
7-0
Reg
0E
0E
0E
0E
0F
0F
0F
0F
0F
Bit
7
6
1
0
7
5
4
3
1-0
Mnemonic
PORT7-6
PORT5-2
BURSTF
CSYNC
PED21
VSEL
CBSEL
VBIEN
HDSEL
Reserved
Function
General purpose Inputs
General purpose Outputs
Burst Flag Output
Composite Sync Output
VBI Pedestal Enable
Vertical Sync Select
CBSEL/PDC Pin Function
VBI Pixel Data Enable
HSYNC Delay
May be left unprogrammed
TMC2490A Identification Registers (Read only)
General Purpose Port Register
Global Control Register
General Control Register
Reserved Registers
Video Output Control Register
Closed-Caption Insertion Registers
7-0
7-0
7
6
5
4
3-0
CCD1
CCD2
CCON
CCRTS
CCPAR
CCFLD
CCLINE
First Byte of CC Data
Second Byte of CC Data
Enable CC Data Packet
Request To Send Data
Auto Parity Generation
CC Field Select
CC Line Select
Field ID Register
Notes:
1. For each register listed above, all bits not specified are
reserved and should be set to logic LOW to ensure proper
operation.
Reserved Registers
REV. 1.0.2 2/27/02
5
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
