PRODUCT SPECIFICATION
TMC2490A
Pin Assignments
SDA/R/W
SA
0
/ADR
SA
1
PD
0
GND
V
DD
PD
1
PD
2
PD
3
PD
4
PD
5
6
5
4
3
2
1
44
43
42
41
18
19
20
21
22
23
24
25
26
27
HSYNC
VSYNC,T/B
CBSEL,PDC
SELC
RESET
V
DD
GND
PXCK
V
DD
V
REF
R
REF
28
SCL/CS
SER
D
7
D
6
D
5
D
4
GND
D
3
D
2
D
1
D
0
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TMC2490A
PD
6
PD
7
V
DD
GND
CHROMA
V
DDA
C
BYP
LUMA
GND
COMPOSITE
GND
65-2490(1)A-02
Pin Descriptions
Pin Name
Clock
PXCK
25
TTL
Pixel Clock Input.
This 27.0 MHz clock is internally divided by 2
to generate the internal pixel clock. PXCK drives the entire
TMC2490A, except the asynchronous microprocessor interface.
All internal registers are strobed on the rising edge of PXCK.
Pixel Data Inputs.
Video data enters the TMC2490A on
PD
7-0
(Figure 1).
Data I/O, General Purpose I/O, Chroma Input Port.
When SER
is HIGH, all control parameters are loaded into and read back
over this 8-bit port. When SER = LOW, D
0
can serve as a
composite sync output, D
1
outputs a burst flag during the back
porch, D
2-5
are General Purpose Outputs, and D
6-7
are General
Purpose Inputs.
Master Reset Input.
Bringing RESET LOW forces the internal
state machines to their starting states and disables all outputs.
Serial/Parallel Port Select.
When SER is LOW, SA
1
in
conjunction with SA
0
selects one of four addresses for the
TMC2490A.
Serial/Parallel Port Select.
When SER is LOW, SA
0
in
conjunction with SA
1
selects one-of-four addresses for the
TMC2490A. When SER is HIGH, this control governs whether the
parallel microprocessor interface selects a table address or
reads/writes table contents.
Pin Number
Value
Pin Function Description
Data Input Port
PD
7-0
38–44, 3
TTL
Microprocessor Interface
D
7-0
9–12, 14–17
TTL
RESET
SA
1
22
4
TTL
TTL
SA
0
, ADR
5
TTL
3
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