PRODUCT SPECIFICATION
TMC22x5yA
Reg Bit Name
Function
Reg Bit Name
Function
V gain, 8 lsbs
0D 7-6 CEST
Chroma error signal
transform
1A 7-0 VG0
1B 7-6 YG0
1B 5-3 UG0
7-0
Y gain, 2 msbs
U gain, 3 msbs
9-8
0D
0D
0D
5
4
3
CESG
Chroma error signal gain
Luma error signal gain
10-8
YESG
1B
2
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Y offset, msb
CESTBY
Chroma error signal
bypass
1B 1-0 VG0
9-8
1C 7-0 YOFF0
1D 7-3
7-0
0D
0D
0D
2
1
0
XFEN
FAST
YWBY
XLUT filter enable
Adaption speed select
Luma weighting bypass
XLUT input select
XLUT special function
Y output select
1D
2
YOFF0
7-0
1E 7-1 SYSPH0
8
1D 1-0 SG0
Msync gain, 2 msbs
7 lsbs of phase
V axis flip
0E 7-6 XIP
6-0
0E 5-4 XSF
0E 3-2 YMUX
0E 1-0 CMUX
1E
0
VAXISO
1F 7-0 SYSPH0
8 msbs of phase
14-7
C output select
Normalized Subcarrier Frequency
0F
0F 6-5 CAT
0F DCES
0F 3-2 IPCF
7
reserved, set to zero
Adaption Threshold
20 7-4 FSC
20 3-0
Bottom 4 bits of f
SC
3-0
reserved, set to zero
4
D1 C C error signal
B R
21 7-0 FSC
22 7-0 FSC
23 7-0 FSC
Lower 8 bits of f
11-4
SC
Comb filter input select
Middle 8 bits of f
19-12
27-20
SC
SC
0F
1
YCCOMP
YC or Composite input
select
Top 8 bits of f
Clamp Control
0F
0
SYNC
Sync processor select
24
24
7
6
DRFSEL
PFLTBY
Clamp pulse enable
Phase filter enable
Int. clamp selection
Clamp bypass
Sync Pulse Generator
10 7-0 STS
11 7-0 STB
12 7-0 BTV
Sync to sync 8 lsbs
Sync to burst
7-0
24 5-4 CLPSEL
1-0
VCLPEN
24 2-0 BAND
24
3
Burst to video
Clamp offset
2-0
25 7-0 CPDLY
13 7-0 AV
14 7-6
Active video line 8 lsbs
reserved, set to zero
Active video line 2 msbs
reserved, set to zero
Sync to sync 3 msbs
reserved, set to zero
7-0
Clamp pulse delay
7-0
Output Format Control
reserved, set to zero
14 5-4 AV
9-8
26 7-6
14
3
26
26
26
5
4
3
LDVIO
LDV clock select
Output clock select
DPC enable
14 2-0 STS
10-8
OPCKS
DPCEN
15
7
15 6-2 VINDO
Number of lines in vertical
window
26 2-0 DPC
Decoder product code
15
15
1
0
VDIV
Action inside VINDO
Action outside VINDO
reserved, set to zero
new field detect delay
SPG input select
Buffered register set 1
Active when BUFFER pin set HIGH
VDOV
27 7-0 SG1
28 7-0 YG1
29 7-0 UG1
2A 7-0 VG1
2B 7-6 YG1
2B 5-3 UG1
Msync gain, 8 lsbs
Y gain, 8 lsbs
7-0
7-0
7-0
7-0
9-8
10-8
16 7-6
16 5-4 NFDLY
16 3-2 SPGIP
16 1-0 MSIP
U gain, 8 lsbs
V gain, 8 lsbs
Mixed sync separator input
select
Y gain, 2 msbs
U gain, 3 msbs
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Buffered register set 0
Active when BUFFER pin set LOW
2B
2
17 7-0 SG0
18 7-0 YG0
19 7-0 UG0
Msync gain, 8 lsbs
Y gain, 8 lsbs
7-0
7-0
7-0
2B 1-0 VG1
9-8
2C 7-0 YOFF1
2D 7-3
7-0
U gain, 8 lsbs
REV. 1.0.0 2/4/03
9
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
