PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions
Global Control Register (00)
7
6
5
4
3
2
1
0
SRST
HRST
SET
DHVEN
STD
Reg
Bit
Name
Description
00
7
SRST
Software reset. When LOW, resets and holds internal state machines and
disables outputs. When HIGH (normal), starts and runs state machines and
enables outputs. This bit is ignored while HRST is high.
00
6
HRST
SET
Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin
is taken LOW. State machines are reset and held. When HRST is low the
RESET pin can be taken HIGH at any time. The state machines remain
disabled until SRST is programmed HIGH. When HRST is high the state
machines are enabled as soon as the RESET pin goes HIGH.
00
5-3
SET pin function. These bits control the set function when the SET pin goes
low.
A = all outputs high-impedance
B = internal state machines
C = burst locked loop
SET
000
001
Function
Reset and hold A, B, & C.
Set output to BLUE and flywheel B & C. (RGB outputs)
Set output to "color" and flywheel B & C (YC C outputs)
B R
010
011
100
101
110
111
Hold A, lock B & C to external input
Reset C only
Reset B & C
Set output to BLUE and lock B & C to input video (RGB output)
Line and pixel grab depending on VMCR
6-0
(reg 30)
Toggle reset function of SET = 010. For each SET = 0 pulse the
chip operation will change from normal to that of SET = 010 or
visa versa.
The first SET pulse after a software or hardware reset, with SET = 111,
causes a toggle to SET = 010.
00
00
2
DHVEN
STD
Output H&V sync enable. Disables DHSYNC and DVSYNC signals when
HIGH.
1-0
Selects video standard. Selects video standard.
SET
00
Function
NTSC
01
reserved
10
PAL/M
11
All PAL standards except PAL/M
REV. 1.0.0 2/4/03
11
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
