PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions
Parameter
Min.
Nom.
Max.
Units
V
V
Power Supply Voltage
4.75
5.0
5.25
V
DD
IH
Input Voltage, Logic HIGH
TTL Compatible Inputs
2.0
V
DD
V
V
Serial Port (SDA and SCL)
Input Voltage, Logic LOW
TTL Compatible Inputs
0.7*V
DD
V
IL
GND
GND
0.8
0.3*V
V
V
Serial Port (SDA and SCL)
Output Current, Logic HIGH
Output Current, Logic LOW
Ambient Temperature, Still Air
DD
I
I
-2.0
4.0
70
mA
mA
°C
OH
OL
T
A
0
Pixel Interface (input)
f
Pixel Rate (CKSEL = 0)
Master Clock Rate = 2X pixel rate (CKSEL = 1)1
10
20
8
18
36
MHz
MHz
ns
CLK
t
t
t
t
t
t
CLOCK pulse width, HIGH
PWHCK
PWLCK
SP
CLOCK pulse width, LOW
13
8
ns
Pixel Data Input Setup Time
ns
Pixel Data Input Hold Time
2
ns
HP
HSYNC, VSYNC, and BUFFER setup time
HSYNC, VSYNC, and BUFFER hold time
5
ns
SP
6
ns
HP
Notes:
1. Tested at f
= 30MHz
CLK
To aid in the understanding of the timing relationship between the PXCK and LDV clock, when the LDV signal is used as the
TMC22x5yA output clock, the following block diagram of the TMC22x5yA output stage is provided.
Data In
PXCK
D
Q
D
Q
G/Y, B/U, and R/V
Output Data
Ck
Ck
2:1
mux
LDV
65-22x5y-78
Figure 42. Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output Stage
REV. 1.0.0 2/4/03
73
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
