PRODUCT SPECIFICATION
TMC22x5yA
Reg
0D
0D
0D
0D
0D
0D
0D
0E
0E
0E
0E
0F
0F
0F
0F
0F
0F
10
11
12
13
14
14
14
14
15
15
15
15
16
16
16
16
Bit
7-6
5
4
3
2
1
0
7-6
5-4
3-2
1-0
7
6-5
4
3-2
1
0
7-0
7-0
7-0
7-0
7-6
5-4
3
2-0
7
6-2
1
0
7-6
5-4
3-2
1-0
Name
CEST
CESG
YESG
CESTBY
XFEN
FAST
YWBY
XIP
XSF
YMUX
CMUX
CAT
DCES
IPCF
YCCOMP
SYNC
STS
7-0
STB
BTV
AV
7-0
AV
9-8
STS
10-8
VINDO
VDIV
VDOV
NFDLY
SPGIP
MSIP
Function
Chroma error signal
transform
Chroma error signal gain
Luma error signal gain
Chroma error signal
bypass
XLUT filter enable
Adaption speed select
Luma weighting bypass
XLUT input select
XLUT special function
Y output select
C output select
reserved, set to zero
Adaption Threshold
D1 C
B
C
R
error signal
Comb filter input select
YC or Composite input
select
Sync processor select
Reg
1A
1B
1B
1B
1B
1C
1D
1D
1D
1E
1E
1F
20
20
21
22
23
24
24
24
24
24
25
26
26
26
26
26
Bit
7-0
7-6
5-3
2
1-0
7-0
7-3
2
1-0
7-1
0
7-0
7-4
3-0
7-0
7-0
7-0
7
6
5-4
3
2-0
7-0
7-6
5
4
3
2-0
Name
VG0
7-0
YG0
9-8
UG0
10-8
VG0
9-8
YOFF0
7-0
YOFF0
8
SG0
7-0
SYSPH0
6-0
VAXISO
SYSPH0
14-7
FSC
3-0
FSC
11-4
FSC
19-12
FSC
27-20
DRFSEL
PFLTBY
CLPSEL
1-0
VCLPEN
BAND
2-0
CPDLY
7-0
Function
V gain, 8 lsbs
Y gain, 2 msbs
U gain, 3 msbs
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Y offset, msb
Msync gain, 2 msbs
7 lsbs of phase
V axis flip
8 msbs of phase
Bottom 4 bits of f
SC
reserved, set to zero
Lower 8 bits of f
SC
Middle 8 bits of f
SC
Top 8 bits of f
SC
Clamp pulse enable
Phase filter enable
Int. clamp selection
Clamp bypass
Clamp offset
Clamp pulse delay
reserved, set to zero
Normalized Subcarrier Frequency
Clamp Control
Sync Pulse Generator
Sync to sync 8 lsbs
Sync to burst
Burst to video
Active video line 8 lsbs
reserved, set to zero
Active video line 2 msbs
reserved, set to zero
Sync to sync 3 msbs
reserved, set to zero
Number of lines in vertical
window
Action inside VINDO
Action outside VINDO
reserved, set to zero
new field detect delay
SPG input select
Mixed sync separator input
select
Output Format Control
LDVIO
OPCKS
DPCEN
DPC
LDV clock select
Output clock select
DPC enable
Decoder product code
Buffered register set 1
Active when BUFFER pin set HIGH
27
28
29
2A
2B
2B
2B
2B
2C
2D
7-0
7-0
7-0
7-0
7-6
5-3
2
1-0
7-0
7-3
VG1
9-8
YOFF1
7-0
SG1
7-0
YG1
7-0
UG1
7-0
VG1
7-0
YG1
9-8
UG1
10-8
Msync gain, 8 lsbs
Y gain, 8 lsbs
U gain, 8 lsbs
V gain, 8 lsbs
Y gain, 2 msbs
U gain, 3 msbs
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
9
Buffered register set 0
Active when BUFFER pin set LOW
17
18
19
7-0
7-0
7-0
SG0
7-0
YG0
7-0
UG0
7-0
Msync gain, 8 lsbs
Y gain, 8 lsbs
U gain, 8 lsbs
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
