TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions
(continued)
Input Processor Control (01)
7
Reserved
Reg
01
01
Bit
7
6
6
IPMUX
Name
Reserved
IPMUX
5
IP8B
4
TDEN
3
TBLK
2
IPCMSB
1
ABMUX
0
CKSEL
Description
Reserved, set to zero.
Input mux control.
Used to select the Video Input Processor, D1, or D2 data
as the VA input to the input processor.
VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is
set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set
HIGH. For YC inputs, the luma data must be passed through the VA input and
chroma through the VB input.
IPMUX should be set LOW for line locked composite inputs.
8 bit input format.
Bottom two bits of inputs VIDEOA
9-0
and VIDEOB
9-0
are
set to zero when HIGH.
TRS detect enable.
When HIGH, the TRS words embedded in incoming
video are used to reset the horizontal and vertical state machines. When LOW
the externally provided or internally generated HSYNC and VSYNC are used
to reset the horizontal and vertical state machines.
TRS blank enable.
Blanks the TRS and AUX data words when HIGH. For line
locked and D1 data, the TRS and AUX data words are set to the luma and
chroma blanking levels as appropriate. For D2 (4*f
SC
) data, the TRS and
AUX data words are set to the sync tip level.
Chroma input msb invert.
The msb of the chroma or C
B
C
R
data are inverted
when HIGH.
AB mux control.
Selects the primary and secondary inputs to the decoder
from the DA and DB outputs of the input processor. When ABMUX is LOW,
DA is selected as the primary and DB as the secondary decoder input.
Input clock rate select.
Set HIGH for line locked clocks and LOW for
subcarrier locked clocks. Line locked clocks should be at twice the pixel data
rate, and the subcarrier clock should be at four times the subcarrier
frequency.
01
01
5
4
IP8B
TDEN
01
3
TBLK
01
01
2
1
IPCMSB
ABMUX
01
0
CKSEL
12
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
