欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMC1175AM7C40 参数 Datasheet PDF下载

TMC1175AM7C40图片预览
型号: TMC1175AM7C40
PDF下载: 下载PDF文件 查看货源
内容描述: 视频A / D转换器的8位, 40 Msps的 [Video A/D Converter 8 bit, 40 Msps]
分类和应用: 转换器光电二极管
文件页数/大小: 18 页 / 438 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
 浏览型号TMC1175AM7C40的Datasheet PDF文件第1页浏览型号TMC1175AM7C40的Datasheet PDF文件第2页浏览型号TMC1175AM7C40的Datasheet PDF文件第3页浏览型号TMC1175AM7C40的Datasheet PDF文件第4页浏览型号TMC1175AM7C40的Datasheet PDF文件第6页浏览型号TMC1175AM7C40的Datasheet PDF文件第7页浏览型号TMC1175AM7C40的Datasheet PDF文件第8页浏览型号TMC1175AM7C40的Datasheet PDF文件第9页  
PRODUCT SPECIFICATION
TMC1175A
Pin Descriptions
Pin Number
Pin Name
Inputs
V
IN
R
T
19
17
23
20
R
T
– R
B
Analog Input.
The input voltage conversion range lies between the
voltages applied to the RT and RB pins.
2.6V
Reference Voltage Top Input.
R
T
is the top input to the reference
resistor ladder. A DC voltage applied to R
T
defines the positive end
of the V
IN
conversion range.
Reference Voltage Bottom Input.
R
B
is the bottom input to the
reference resistor ladder. A DC voltage applied to R
B
defines the
negative end of the V
IN
conversion range.
Reference Voltage Top Source.
VR+ is the internal pull-up
reference resistor for self-bias operations.
Reference Voltage Bottom Source.
VR- is the internal pull-down
reference resistor for self-bias operations.
CMOS
CMOS
Output Enable.
(CMOS-compatible) When LOW, D
7-0
are enabled.
When HIGH, D
7-0
are in a high-impedance state.
Convert (Clock) Input.
(CMOS-compatible) V
IN
is sampled on the
falling edge of CONV.
Data Outputs (D7 = MSB).
Eight-bit CMOS- and TTL-compatible
digital outputs. Data is output following the rising edge of CONV.
Analog Supply Voltage.
Independent +5 volt power connection to
analog comparator circuits.
Digital Supply Voltage.
Independent +5 volt power connection to
digital error correction and output drivers.
Analog Ground.
Connect to the system analog ground plane.
Digital Ground.
Connect to the system analog ground plane.
Not Connected.
M7
R3
Pin Type Pin Function Description
R
B
23
27
0.6V
VR+
VR–
OE
CONV
Outputs
D
7-0
Power
V
DDA
V
DDD
A
GND
D
GND
No Connect
N/C
16
22
1
12
19
26
2
14
10–3
12–9,
7–4
17, 18,
21
13, 16
24, 25
3, 28
1, 8, 15,
22
CMOS/
TTL
+5V
+5V
0.0V
0.0V
open
14, 15, 18
11, 13
20, 21
2, 24
Bandwidth Specification Notes
The specification for bandwidth of an A/D converter is some-
what different from the normal frequency-response specifi-
cation used in amplifiers and filters. An understanding of the
differences will help in selecting converters properly for par-
ticular applications.
A/D conversion comprises two distinct processes:
sampling
and
quantizing. Sampling
is “grabbing” a snapshot of the
input signal and holding it steady for quantizing. The
quan-
tizing
process is approximating the analog input, which may
be any value within the conversion range, with its nearest
numerical value. While sampling is a high-frequency pro-
cess, quantizing operates on a dc signal, held steady by the
track/hold circuit. Therefore, the sampling process is what
relates to the dynamic characteristics of the converter.
REV. 1.3.3 2/28/02
Sampling involves an
aperture time,
the time during which
the track/hold is trying to capture the input signal and settle
on a dc value to hold. It is analogous to the shutter speed of a
camera: the shorter the aperture (or faster the shutter) the less
the signal will be blurred, and the less uncertainty there will
be in the quantized value.
For example, a 10 MHz sinewave with a 1V peak amplitude
(2Vp-p) has a maximum slew rate of 2πfA at zero crossing,
or 62.8V/µs. With an 8-bit A/D converter, q (the quantization
step size) = 2V/255 = 7.8mV. The input signal will slew one
LSB in 124ps. To limit the error (and noise) contribution due
to
aperture effects
to 1/2LSB, the aperture must be shorter
than 62ps.
5