PRODUCT SPECIFICATION
TMC1175A
Table 1. Output Coding
Input Voltage
R
T
+ 1 LSB
R
T
R
T
– 1 LSB
•••
R
B
+ 128 LSB
R
B
+ 127 LSB
•••
R
B
+ 1 LSB
R
B
R
B
– 1 LSB
Note:
1. LSB = (R
T
– R
B
) / 255
Output
FF
FF
FE
•••
80
7F
•••
01
00
00
remain valid for t
HO
(Output Hold Time), satisfying any
hold time requirement of the receiving circuit. The new data
become valid t
DO
(Output Delay Time) after this rising edge
of CONV.
The outputs of the TMC1175A are CMOS- and TTL-com-
patible, and are capable of driving four low-power Schottky
TTL (54/74LS) loads. An Output Enable control, OE, places
the outputs in a high-impedance state when HIGH. The out-
puts are enabled when OE is LOW.
Power and Ground
To minimize noise injection into the analog section, V
DDA
may be connected to a separate regulated +5 volt supply.
V
DDD
may be connected to a digital supply. Power up
sequence is immaterial. Latch-up will not occur.
A
GND
and D
GND
pins should be connected to a common
ground plane. For optimum performance treat analog and
digital PWB traces as transmission lines. Route analog
connections cleanly to the TMC1175A. Segregate digital
connections and if necessary terminate clocks to eliminate
ringing. Prevent digital returm currents from flowing across
analog input sections of the TMC1175A.
Digital Inputs and Outputs
Sampling of the applied input signal takes place on the
fall-
ing
edge of the CONV signal (Figure 2). The output word is
delayed by 2 1/2 CONV cycles. It is then available after the
rising
edge of CONV. The previous data on the output
t
STO
Sample N
Sample N+1
t
PWL
CONV
t
DO
D
7-0
ORP
ORN
t
HO
Data N–3
Data N–2
t
DIS
Hi-Z
Data N–1
t
ENA
t
PWH
1/f
S
Sample N+2
Sample N+3
V
IN
Data N
OE
24455A
Figure 2. Conversion Timing
REV. 1.3.3 2/28/02
3
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
