TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
If LE is high and LE low in the SPT9691, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
pdH
(Q or Q ). The input signal must be
maintained for a time t
s
(set-up time) before the LE falling
edge and
LE
rising edge and held for time t
H
after the falling
edge for the comparator to accept data. After t
H
, the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t
pL
is needed for strobe opera-
tion, and the output transitions occur after a time of t
pLOH
or
t
pLOL
.
Figure 1 - Timing Diagram
Latch Enable
50%
Latch Enable
t
H
t
S
Differential
Input Voltage
V
OD
Output Q
t
pdL
t
pLOH
50%
VRef ± VOS
tpL
50%
Output Q
t
pdH
V
IN
+=300 mV, V
OD
=150 mV
t
pLOL
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t
s
will be detected
and held; those occurring after t
H
will not be detected. Changes between t
S
and t
H
may not be detected.
SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output LOW to HIGH transition.
t
pdL
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
t
H
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
t
pL
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
t
S
V
OD
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
SPT9691
4
10/6/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
