Figure 3 - Typical Interface Circuit
Figure 4 - Typical Interface With Hysteresis
V
V
EE
GND
CC
V
O
V
V
CC
EE
GND
.1 µF
V
IN
Noninverting
Input
.1 µF
V
Q OUTPUT
Q OUTPUT
+
-
IN
V
REF
Noninverting
Input
Inverting
Input
R
R
L
L
V
IN
Q Output
Q Output
50 Ω
50 Ω
+
-
LE
V
LE
V
.1 µF
Ref
Inverting
Input
-2 V
300 Ω
V
LE
R
R
L
50 Ω
LE
-5.2 V
L
300 Ω
50 Ω
-5.2 V
LE
LE
.1 µF
0.1 µF
100 Ω
100 Ω
-2 V
ECL
= Represents line termination.
Hysteresis is obtained by applying a DC bias to the LE pin.
V
=
-1.3 V ±100 mV, V = -1.3 V.
LE
LE
Represents line termination.
Figure 5 - Equivalent Input Circuit
Figure 6 - AC Test Fixture
+
V
CC
V
IN
MONITOR
(+5.0 V)
GND
V
CC
15 µF
Q
3
6
L1
L3
0.1 µF
R
R
2
1
50
Q
50
50
6
6
9
L2
C
V+
Q
+
-
C
SEMI-
RIGID
SEMI
RIGID
V
+
-
IN
1 pF
+
V
IN
1 pF
OUT
IN
100
100
6
6
Q
DUT 4
V
11
Q
V-
OUT
SEMI-
RIGID
V
SEMI
IN
-
RIGID
LE
R
100
LE
IN
V
Q
7
Q
IN
IN
1
0.1 µF
0.1 µF
100 Ω
50
50
Q
Q
5
4
L2
SAMPLING
SCOPE
V
PRE
PRE
0.1 µF
R
100
100
IN
V
V
100 Ω
V
R2
50
50
L1
L1
6
6
6
6
Q
Q
Q
Q
Q
12
15 µF
TANT
15 µF
2
6
8
10
V
R1
-
-
+
+
R
R
R
R
R
7
3
4
5
6
V
VEE
(-5.2 V)
VpD
(-4.0 V)
LE
MONITOR
LE
LE
LE
MONITOR
EE
Figure 7 - Output Circuit
Figure 8 - Test Load
R
z
R
7
R
8
50 Ω Coax
240 Ω
240 Ω
50 Ω
Q
Q
24
23
R
L
R
Z
Q Output
Q Output
100 Ω
100 Ω
V
V
2
1
Q
Q
21
22
4.5 mA
V
pd
(-4.0 V)
SPT9687
5
3/21/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
