ELECTRICAL SPECIFICATIONS
T
= +25 °C, V
= +5.0 V, V = -5.20 V, R = 50 Ohm, unless otherwise specified.
A
CC
EE
L
TEST
CONDITIONS
TEST
LEVEL
SPT9687
TYP
PARAMETERS
MIN
MAX
UNITS
2
AC ELECTRICAL CHARACTERISTICS
Latch to Output Delay
Latch Pulse Width
50 mV OD
IV
V
3
ns
ns
ns
ns
ns
2
Latch Hold Time
IV
V
0.5
Rise Time
20% to 80%
20% to 80%
1.2
1.2
Fall Time
1
V
R = Source impedance.
S
100 mV input step.
2
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
Unless otherwise noted, all tests are pulsed
tests; therefore, T = T = T .
J
C
A
Figure 1 - Timing Diagram
LATCH ENABLE
LATCH ENABLE
50%
tH
tpL
tS
V
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
REF
OD
tpLOH
tpdL
OUTPUT Q
OUTPUT Q
50%
50%
tpdH
tpLOL
V
+ = 100 mV (p-p), V = 50 mV
OD
IN
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t will be detected
s
and held; those occurring after t will not be detected. Changes between t and t may not be detected.
H
s
H
SPT9687
3
3/21/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
