Figure 3 - Typical Interface Circuit
Figure 4 - Typical Interface With Hysteresis
VCC GND VEE
VO
VCC
GND
VEE
.1 µF
VIN
.1 µF
VIN
VREF
Noninverting
Input
+
-
Inverting
Input
Q OUTPUT
Q OUTPUT
VIN
VRef
Noninverting
Input
+
Inverting
Input
Q Output
Q Output
LE
LE
RL
50
Ω
RL
50
Ω
.1 µF
-
RL
50
Ω
LE
LE
-2 V
RL
50
Ω
-2 V
300
Ω
VLE
VLE
300
Ω
-5.2 V
-5.2 V
.1 µF
100
Ω
0.1 µF
100
Ω
ECL
= Represents line termination.
Hysteresis is obtained by applying a DC bias to the LE pin.
V
LE
= -1.3 V ±100 mV, V
LE
= -1.3 V.
Represents line termination.
Figure 5 - Equivalent Input Circuit
Figure 6 - AC Test Fixture
V +
IN
MONITOR
V
CC
(+5.0 V)
GND
VCC
15 µF
L1
6
SEMI
RIGID
Q3
L3
R
C
1
R 2
Q9
6
V +
IN
0.1 µF
50
50
L2
6
SEMI
RIGID
V
6
SEMI
RIGID
+
IN
1 pF
IN
1 pF
Q11
C
SEMI-
RIGID
6
100
SEMI-
RIGID
+
V+
Q
Q
100
0.1 µF
100
50
OUT
V -
IN
DUT
4
-
LE
LE
V-
V
OUT
-
R
V
IN
IN
Q1
Q
Q4
Q5
7
50
0.1 µF
100
Ω
V
L2
PRE
100
100
0.1 µF
50
SAMPLING
SCOPE
R
VIN
IN
V
PRE
100
Ω
V
R2
L1
50
50
L1
SEMI
RIGID
SEMI
RIGID
VR1
Q2
Q6
Q8
Q
10
Q
12
SEMI
RIGID
6
SEMI
RIGID
6
6
6
15 µF
15 µF
TANT
-
+
+
-
R3
V
EE
R4
R5
R6
R7
LE
MONITOR
LE
LE
LE
MONITOR
V
EE
(-5.2 V)
V
pD
(-4.0 V)
Figure 7 - Output Circuit
R7
240
Ω
R8
240
Ω
Figure 8 - Test Load
Rz
50
Ω
Coax
50
Ω
Q24
Q23
RL
Q Output
V1
Q21
Q22
V2
Q Output
RZ
100
Ω
100
Ω
4.5 mA
Vpd
(-4.0 V)
SPT9687
5
3/21/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
