ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
V
CC
= +5.0 V, V
EE
= -5.20 V, R
L
= 50 Ohm, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT9687
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS
2
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
Fall Time
1
R
S
= Source impedance.
2
100 mV input step.
50 mV OD
IV
V
IV
2
3
ns
ns
0.5
1.2
1.2
ns
ns
ns
20% to 80%
20% to 80%
V
V
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all tests are pulsed
tests; therefore, T
J
= T
C
= T
A
.
Figure 1 - Timing Diagram
LATCH ENABLE
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
50%
LATCH ENABLE
t
S
DIFFERENTIAL
INPUT VOLTAGE
V
OD
t
pdL
OUTPUT Q
50%
t
pLOH
t
H
tpL
VREF ± VOS
50%
OUTPUT Q
t
pdH
t
pLOL
V
IN
+ = 100 mV (p-p), V
OD
= 50 mV
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t
s
will be detected
and held; those occurring after t
H
will not be detected. Changes between t
s
and t
H
may not be detected.
SPT9687
3
3/21/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
