Figure 2 – Typical Interface Circuit
CLK IN
DOV
SS
FB2
OTR
D11
D10
D9
Out of Range Bit
MSB
DV
SS
CLK
DV
DD
AV
SS
V
IN
R
FB3
+
SPT7938
+A5
+
AV
DD
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
A
IN
+A5
U1
+
V
IN
RV
SS
V
RHS
V
RHF
V
RLF
V
RLS
28
TK11240B
Ext V
REF
(+4 V)
EN
DOV
DD
1
FB1
+
+D3/5V
+A5
+
10
+A5
AGND
+D3/5V
+D3/5
+
10
+D3/5
DGND
Notes:
1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad
surface-mount chip capacitors. They need to be placed as close to the pin as possible.
2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors.
3) FB1, FB2 and FB3 are ferrite beads. Place FB1 as close to the SPT7938 as possible.
4) U1 is a TOKO regulator, TK112XXB. XX is the regulated output voltage ranging from
1.3 V to 4.8 V with 100 mV increment. For example, TK11240B is a 4.0 V regulator.
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical inter-
face requirements when using the SPT7938 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical performance
criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital (DV ) and the ana-
DD
log (AV
DD
) supply voltages on the SPT7938 be derived from
a single analog supply as shown in figure 2. A separate digi-
tal supply should be used for the digital output driver supply
(OV
DD
) and all interface circuitry. CADEKA suggests using
this power supply configuration to prevent a possible latch-
up condition on power up. In addition, the power supplies
must be powered up before the analog input is applied.
SPT7938
5
5/24/00
Interfacing Logic
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
