ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
V
DD
............................................................................ +6 V
Input Voltages
Analog Input .................................... –0.5 V to V
DD
+0.5 V
CLK Input ................................................................... V
DD
AGND – DGND ..................................................
±100
mV
Output
Digital Outputs ....................................................... 10 mA
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
Temperature
Operating Temperature ............................. –40 to +85
°C
Junction Temperature ......................................... +175
°C
Lead Temperature, (soldering 10 seconds) ........ +300
°C
Storage Temperature ............................... –65 to +150
°C
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, V
DD
=+5.0 V, ƒ
S
=40 MSPS, V
IN
=0 to 4 V, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
–Full-Scale Error
1
+Full-Scale Error
1
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
Over-Voltage Recovery Time
2
Reference Input
Resistance
Voltage Range
V
RHS
V
RLS
V
RHS
– V
RLS
Dynamic Performance
Effective Number of Bits
ƒ
IN
=3.58 MHz
ƒ
IN
=3.58 MHz
Signal-to-Noise Ratio
(without Harmonics)
ƒ
IN
=3.58 MHz
ƒ
IN
=3.58 MHz
1
The
2
TEST
CONDITIONS
TEST
LEVEL
MIN
12
SPT7938
TYP
MAX
UNITS
Bits
V
V
VI
VI
V
V
V
V
V
VI
V
IV
V
V
V
RLS
±3
±1
Guaranteed
V
RHS
25
5.0
250
0.035
–0.12
40
1
14
1.0
5.0
25
LSB
LSB
V
IN
= 2 V
PP
V
kΩ
pF
MHz
%FS
%FS
MHz
MHz
Clock Cycles
ns
ps(p-p)
ns
Ω
V
V
V
VI
IV
IV
V
420
3.0
0.0
2.0
465
520
V
DD
2.0
5.0
4.0
T
A
= +25
°C
T
A
= T
MIN
to T
MAX
T
A
= +25
°C
T
A
= T
MIN
to T
MAX
I
IV
9.9
9.4
10.1
10.1
Bits
Bits
I
IV
61.2
58.0
62.5
62.5
dB
dB
full-scale range spans the reference ladder sense pins, V
RHS
and V
RLS
. Refer to the Voltage Reference section for discussion.
Due to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒ
CLK
= 40 MHz).
SPT7938
2
5/24/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
