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SPT7850SIS 参数 Datasheet PDF下载

SPT7850SIS图片预览
型号: SPT7850SIS
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 20 MSPS , 140 mW的A / D转换器 [10-BIT, 20 MSPS, 140 mW A/D CONVERTER]
分类和应用: 转换器
文件页数/大小: 13 页 / 191 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
AV
DD
...................................................................... +6 V
DV
DD
..................................................................... +6 V
Input Voltages
Analog Input .............................. –0.5 V to AV
DD
+0.5 V
V
REF
.............................................................. 0 to AV
DD
CLK Input ............................................................... V
DD
AV
DD
– DV
DD
.................................................. ±100 mV
AGND – DGND .............................................. ±100 mV
Output
Digital Outputs ................................................... 10 mA
Temperature
Operating Temperature ............................ –40 to 85 °C
Junction Temperature ........................................ 175 °C
Lead Temperature, (soldering 10 seconds) ....... 300 °C
Storage Temperature ............................ –65 to +150 °C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, AV
DD
=DV
DD
=OV
DD
=+5.0 V, V
IN
=0 to 4 V, ƒ
CLK
=40 MHz, ƒ
S
=20 MSPS, V
RHS
=4.0 V, V
RLS
=0.0 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
No Missing Codes
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
Reference Input
Resistance
Bandwidth
Voltage Range
V
RLS
V
RHS
V
RHS
– V
RLS
∆(V
RHF
– V
RHS
)
∆(V
RLS
– V
RLF
)
Reference Settling Time
V
RHS
V
RLS
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
Dynamic Performance
Effective Number of Bits (ENOB)
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10.3 MHz
Signal-to-Noise Ratio (SNR)
(without Harmonics)
ƒ
IN
= 3.58 MHz
ƒ
IN
= 10.3 MHz
1
SPT7850SCN
TEST
CONDITIONS
TEST
LEVEL
MIN
10
SPT7850
TYP
MAX
UNITS
Bits
100 kHz clock rate
1
V
V
VI
VI
IV
V
V
V
V
VI
V
IV
IV
V
V
V
V
V
VI
V
IV
V
V
20
50
12
5
30
V
RLS
50
5.0
100
±2.0
±2.0
400
100
0
3.0
1.0
500
150
600
2.0
AV
DD
5.0
±1.0
±0.5
Guaranteed
V
RHS
LSB
LSB
(Small Signal)
V
kΩ
pF
MHz
LSB
LSB
MHz
V
V
V
mV
mV
Clock Cycles
Clock Cycles
MHz
kHz
Clock Cycles
ns
ps (p-p)
4.0
90
75
15
20
VI
VI
VI
VI
53
52
8.8
8.5
56
55
Bits
Bits
dB
dB
is screened for DC accuracy tests at 100 kHz. SPT7850SIS and SPT7850SCT are screened for DC accuracy tests at 35 MHz.
SPT7850
2
6/15/01