Figure 2 – Typical Interface Circuit
Ref In
(+4 V)
V
RHF
V
RHS
V
RLS
V
RLF
V
IN
V
IN
V
CAL
CLK IN
CLK
DAV
AV
DD
AGND
D10
D9
D8
D7
D6
D5
OV
DD
OGND
D4
D3
D2
D1
D0
EN
DGND* DV
DD
SPT7850
3.3/5
Interfacing
Logics
3.3/5
+A5
Enable/Tri-State
(Enable = Active Low)
L1
DGND
3.3/5
+A5
AGND
+
10 µF
+5 V
Analog
+5 V
Analog
RTN
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
10 µF
+5 V
Digital
RTN
+5 V
Digital
+
NOTES: 1) L1 is to be located as closely to the device as possible.
2) All capacitors are 0.1 µF surface-mount unless otherwise specified.
3) L1 is a 10 µH inductor or a ferrite bead.
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical in-
terface requirements when using the SPT7850 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in
the block diagram. The design contains eight identical
successive approximation ADC sections, all operating in
parallel, a 16-phase clock generator, an 11-bit 8:1 digital
output multiplexer, correction logic, and a voltage refer-
ence generator that provides common reference levels for
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
CADEKA suggests that both the digital and the analog sup- signal in sequence. Each ADC uses 16 clock cycles to
ply voltages on the SPT7850 be derived from a single ana- complete a conversion. The clock cycles are allocated as
log supply as shown in figure 2. A separate digital supply shown in table II.
should be used for all interface circuitry. CADEKA suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
SPT7850
7
6/15/01