Figure 4 - Single Shot Mode Timing Diagram
t
SC
Start Convert
Latch
MSB
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
High Z State
Clock
Serial Data Out
A9
MSB
Start
Conversion
Sample
Analog Input
A8
A7
A6
A5
A4
A3
A2
A1
A0
LSB
Figure 5 - Synchronous Mode Timing Diagram
t
SC
t
SC
Start Convert
Latch
MSB
Latch
MSB
Clock
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
13
A
14
A
15
A
16
A
1
B
2
B
3
B
4
B
5
B
Serial Data Out
High Z State
A9
MSB
Start
Sample
Analog Input
A
A8
A7
A6
A1
A0
LSB
Sample
Analog Input
B
B9
MSB
Figure 6 - Free Run Mode Timing Diagram
Start Convert
Latch
MSB
Clock
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
1
3
A
1
4
A
1
B
2
B
3
B
4
B
5
B
6
B
7
B
Serial Data Out
A9
MSB
Start
Sample
Analog Input
A
A8
A7
A6
A1
A0
LSB
Sample
Analog Input
B
B9
MSB
B8
B7
Figure 7 - Typical Interface Circuit
VREF+
.01 µF
VREF+
0V
VIN
Analog In
Data Out
VDD
Figure 8 - Data Output Timing
t
d
=8 ns
t
d
=8 ns
t
d
=8 ns
t
d
=8 ns
REF IN
+VDD
.01 µF
+VDD
0V
Clock
4
A
5
A
1
3
A
1
4
A
VREF-
Clock
+VDD
0V
Data Out
Ground
SC
+VDD
0V
A9
MSB
A1
A0
LSB
SPT7830
6
12/29/99
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
