GENERAL DESCRIPTION AND OPERATION
The SPT7830 is a 10-bit analog-to-digital converter that
uses a successive approximation architecture to perform
data conversion. Each conversion cycle is 14 clocks in
length. When the Not Start Convert (
SC
) line is held low,
conversion begins on the next rising edge of the input clock.
When the conversion cycle begins, the data output pin is
forced low until valid data output begins.
The first two clock cycles are used to perform internal offset
calibrations and tracking of the analog input. The analog input
is then sampled using an internal track-and-hold amplifier on
the falling edge of the third clock cycle. On clock cycles 4
through 14, a 10-bit successive approximation conversion is
performed, and the data is output starting with the MSB.
Serial data output begins with output of the MSB. See the
Data Output Timing section for details. Each bit of the data
conversion is sequentially determined and placed on the
data output pin at the clock rate. This process continues until
the LSB has been determined and output. At this point, if the
SC
line is high, the data output pin will be forced into a high
impedance state, and the converter will go into an idle state
waiting for the
SC
line to go low. This is referred to as Single
Shot Mode. See Modes of Operation for details.
If the
SC
is either held low through the entire 14 clock
conversion cycle (free run mode) or is brought low prior to
the trailing edge of the fourteenth clock cycle (synchronous
mode), the data output pin goes low and stays low until valid
data output begins. Because the chip has either remained
selected in the free run mode or has been immediately
selected again in the synchronous mode, the next conversion
cycle begins immediately after the fourteenth clock cycle of
the previous conversion. See Modes of Operation for details.
should be taken to ensure that the LSB is latched into an
external latch with the proper amount of set and hold time.
DATA OUTPUT CODING
The coding of the output is straight binary. (See table I.)
Table I - Data Output Coding
ANALOG INPUT
+FS -1/2 LSB
+1/2 FS
+1/2 LSB
V
REF-
OUTPUT CODE D9 - DO
11
1111
111Ø
ØX
XXXX
XXXX
OO
OOOO
OOOØ
OO
OOOO
OOOO
Ø indicates the flickering bit between logic O and 1.
X indicates the flickering bit between logic 1 and O.
ANALOG INPUT AND REFERENCE SETTLING TRACK
AND HOLD TIMING
Figure 9 shows the timing relationship between the input
clock and
SC
versus the analog input tracking and reference
settling. The analog input is tracked from the fourteenth clock
cycle of the previous conversion to the third clock cycle of the
current conversion. On the falling edge of the third clock
cycle, the analog input is held by the internal sample-and-
hold. After this sample, the analog input may vary without
affecting data conversion.
The reference ladder inputs (V
REF
+ and V
REF
-) may be
changed starting on the falling edge of the thirteenth clock
cycle of the previous conversion and must be settled by the
falling edge of the third clock cycle of the current conversion.
VOLTAGE REFERENCE AND ANALOG INPUT
The SPT7830 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
The V
REF
+ can be a maximum of 2/3 V
DD
. For example, if
V
DD
= +5 V, then V
REF
+ max = (2/3) * 5 V = +3.3 V. The lower
side of the ladder is typically tied to AGND (0.0 V), but can be
run up to a voltage that is 1/10th of V
DD
below V
REF
+:
V
REF
- max. = V
REF
+ - (1/10) * V
DD
.
For example,
if V
DD
= +5 V and V
REF
+ = 3 V, then
V
REF
- max = 3 V - (1/10)* 5 V = 2.5 V.
The +Full Scale (+FS) of the analog input is expected to be 6%
of [(V
REF
+) - (V
REF
-)] below V
REF
+ and the -Full Scale (-FS)
of the analog input is expected to be 4% of [(V
REF
+) - (V
REF
-)]
above V
REF
-. (See figure 1.)
Therefore,
Analog +FS = V
REF
+ - 0.06 * [(V
REF
+) - (V
REF
-)], and
Analog -FS = V
REF
- +0.04 * [(V
REF
+) - (V
REF
-)].
For example,
if V
REF
+ = 3 V and V
REF
- = 0 V, then
Analog +FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and
Analog -FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V.
TYPICAL INTERFACE CIRCUIT
CLOCK INPUT
The SPT7830 requires a 50%
±10%
duty cycle clock running
at 14 times the desired sample rate. The clock may be
stopped in between conversion cycles without degradation
of operation (single shot type of operation); however, the
clock should remain running during a conversion cycle.
POWER SUPPLY
The SPT7830 requires only a single supply and operates
from 3.0 V to 5.0 V. CADEKA recommends that a 0.01
µF
chip
capacitor be placed as close as possible to the supply pin.
DATA OUTPUT SET UP AND HOLD TIMING
As figure 8 shows, all of the data output bits (except the LSB)
remain valid for a duration equivalent to one clock period and
delayed by 8 ns after the falling edge of clock. Because the
data converter enters into a next conversion ready state at
the leading edge of clock 14,
the LSB bit is valid for a
duration equivalent to only the clock pulse width low
and delayed by 8 ns after the falling edge of clock.
Care
SPT7830
4
12/29/99
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
