tolerance of 0.6% or
±
0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to 150
mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between V
FT
and
V
FB
. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the V
FB
voltage to the desired level. R1 and
R4 should be adjusted such that V
ST
and V
SB
are exactly
+2.0 V and -2.0V respectively.
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is
±
20% of
the recommended reference voltages of V
FT
and V
FB
. How-
ever, because the device is laser trimmed to optimize perfor-
mance with
±
2.5 V references, the accuracy of the device will
degrade if operated beyond a
±
2% range.
The following errors are defined:
+FS error = top of ladder offset voltage =
∆(+FS
-V
ST
+1 LSB)
-FS error = bottom of ladder offset voltage =
∆(-FS
-V
SB
-1 LSB)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
ANALOG INPUT
V
IN1
and V
IN2
are the analog inputs. Both inputs are tied to
the same point internally. Either one may be used as an
analog input “sense” and the other for an input “force." The
inputs can also be tied together and driven from the same
source. The full scale input range will be 80% of the reference
voltage or
±2
volts with V
FB
=-2.5 V and V
FT
=+2.5 V.
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due the
SPT7810’s extremely low input capacitance of only 5 pF and
very high input resistance of 300 kΩ. For example, for an input
signal of
±
2 V p-p with an input frequency of 10 MHz, the peak
output current required for the driving circuit is only 628
µA.
CLOCK INPUT
The clock inputs (CLK,
CLK
) are designed to be driven
differentially with ECL levels. The clock may be driven single
ended since
CLK
is internally biased to -1.3 V.
CLK
may be
left open, but a .01
µF
bypass capacitor to AGND is recom-
mended. As with all high speed circuits, proper terminations
are required to avoid signal reflections and possible ringing
that can cause the device to trigger at an unwanted time.
The CLK pulse width (tpwH) must be kept between 10 ns and
300 ns to ensure proper operation of the internal track-and-hold
amplifier. (See timing diagram.) When operating the SPT7810
at sampling rates above 3 MSPS, it is recommended that the
clock input duty cycle be kept at 50% to optimize performance.
The analog input signal is latched on the rising edge of the CLK.
DIGITAL OUTPUTS
The format of the output data (D0-D9) is straight binary.
These outputs are ECL with the output circuit shown in
figure 4. The outputs are latched on the rising edge of CLK
with a propagation delay of 4 ns. There is a one clock cycle
latency between CLK and the valid output data (see timing
diagram). These digital outputs can drive 50 ohms to ECL
levels when pulled down to -2 V. The total specified power
dissipation of the device does not include the power used by
these loads. The additional power used by these loads can
vary between 10 and 300 mW typically (including the overrange
load) depending on the output codes. If lower power levels
are desired, the output loads can be reduced, but careful
consideration to the capacitive loads in relation to the oper-
ating frequency must be considered.
Table II - Output Data Information
ANALOG INPUT
>+2.0 V + 1/2 LSB
+2.0 V -1 LSB
0.0 V
-2.0 V +1 LSB
<-2.0 V
OVERRANGE
D1O
1
O
O
O
O
OUTPUT CODE
D9-DO
11 1111
11 1111
1111
111Ø
ØØ ØØØØ ØØØØ
OO OOOO OOOØ
OO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
Figure 3 - Output Circuit
AGND
DGND
Data Out
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at logic 1
as long as D10 remains at logic 1. This feature makes it
possible to include the SPT7810 into higher resolution systems.
EVALUATION BOARD
The EB7810 evaluation board is available to aid designers in
demonstrating the full performance of the SPT7810. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7810 is
also available. Contact the factory for price and availability.
SPT7810
8
3/11/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
