Figure 2 - Ladder Force/Sense Circuit
1
AGND
Figure 3 - Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
+4.0 V
External
Reference
VRHS
(+3.91 V)
90 mV
+
-
2
R/2
VRHF
VRHS
R
3
R
4
5
+
-
N/C
R
R=30
Ω
(typ)
All capacitors are 0.01 µF
R
VRLS
R
6
VRLF
VIN
VRLS
(0.075 V)
VRLF (AGND)
0.0 V
R
7
75 mV
R/2
All capacitors are 0.01 µF
In cases where wider variations in offset and gain can be
tolerated, V
Ref
can be tied directly to V
RHF
and AGND can be
tied directly to V
RLF
as shown in figure 3. Decouple force and
sense lines to AGND with a .01
µF
capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The reference ladder circuit shown in figure 3 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
ladder, the voltage drop from V
RHF
to V
RHS
is not equivalent
to the voltage drop from V
RLF
to V
RLS
.
Typically, the top side voltage drop for V
RHF
to V
RHS
will
equal:
V
RHF
- V
RHS
= 2.25 % of (V
RHF
- V
RLF
) (typical),
and the bottom side voltage drop for V
RLS
to V
RLF
will equal:
V
RLS
- V
RLF
= 1.9 % of (V
RHF
- V
RLF
) (typical).
Figure 3 shows an example of expected voltage drops for a
specific case. Vref of 4.0 V is applied to V
RHF
and V
RLF
is tied
to AGND. A 90 mV drop is seen at V
RHS
(= 3.91 V) and a
75 mV increase is seen at V
RLS
(= 0.075 V).
ANALOG INPUT
V
IN
is the analog input. The input voltage range is from V
RLS
to V
RHS
(typically 4.0 V) and will scale proportionally with
respect to the voltage reference. (See voltage reference
section.)
The drive requirements for the analog inputs are very minimal
when compared to most other converters due to the SPT7734's
extremely low input capacitance of only 5 pF and very high
input resistance in excess of 50 kΩ.
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 4.
CALIBRATION
The SPT7734 uses an auto calibration scheme to en-
sure 8-bit accuracy over time and temperature. Gain and
offset errors are continually adjusted to 8-bit accuracy during
device operation. This process is completely transparent to
the user.
Upon power-up, the SPT7734 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 8-
bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power-up
of 250
µsec
(for a 40 MHz clock). Once calibrated, the
SPT7734 remains calibrated over time and temperature.
Since the calibration cycles are initiated on the rising edge of
the clock, the clock must be continuously applied for the
SPT7734 to remain in calibration.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge condi-
tions without degrading analog transition times.
SPT7734
6
1/27/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
