OPERATION
The SPT7710 has 256 preamp/comparator pairs that are
each supplied with the voltage from V
RTF
to V
RBF
divided
equally by the resistive ladder as shown in the block dia-
gram. This voltage is applied to the positive input of each
preamplifier/comparator pair. An analog input voltage ap-
plied at V
IN
is connected to the negative inputs of each
preamplifier/comparator pair. The comparators are then
clocked through each comparator’s individual clock buffer.
When CLK pin is in the low state, the master or input stage
of the comparators compares the analog input voltage to
the respective reference voltage. When CLK changes
from low to high, the comparators are latched to the state
prior to the clock transition and output logic codes in
Figure 3 – Timing Diagram
sequence from the top comparators, closest to V
RTF
(0 V),
down to the point where the magnitude of the input signal
changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decod-
ers when CLK is changed from high to low.
At the output of the decoders is a set of four 7-bit latches
that are enabled (track) when CLK changes from high to
low. From here, the outputs of the latches are coded into
6 LSBs from 4 columns, and 4 columns are coded into
2 MSBs. Next are the MINV and LINV controls for output
inversions, which consist of a set of eight XOR gates.
Finally, 8 ECL output latches and buffers are used to drive
the external loads. The conversion takes one clock cycle
from the input to the data outputs.
N
Analog Input
V
IN
t
PW1
Clock CLK
CLK
t
PW0
N+2
N+1
Master
Comparator Output
6 Bit Latch Output
8 Bit Latch Output
Data Output D0D7
Overrange D8
Data Ready
t
D
N1
N
N+1
Timing for PGA and Cerquad Packages Only
8
Internal Timing
SPT7710
8/17/01
Slave
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
