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SPT7710AIQ 参数 Datasheet PDF下载

SPT7710AIQ图片预览
型号: SPT7710AIQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8 - BIT , 150 MSPS ,FLASH A / D转换器 [8-BIT, 150 MSPS, FLASH A/D CONVERTER]
分类和应用: 转换器
文件页数/大小: 12 页 / 224 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Figure 1 – Typical Interface Circuit 1
L
*See below
+
U1
–
Voltage
Limiter
Analog Input
Can Be Either
Force Or Sense
V
IN
V
RTF
Preamp
Comparator
256
V
EE
2.2 µF
AGND
.01 µF
–5.2 V
LINV
MINV
R
T
MSB D7
Clock
Buffer
255
D6
152
Typical Voltage Limiter
RS
49.9
D1
D2
151
D5
–5.2
D1=D2=HP, 1N 5712
VR2
.01 µF
127
128
D4
256 To
8-Bit
Encoder
ECL
Latches
And
Buffers
D3
64
D2
63
V
EE
2
D1
VRef
–2 V
10
2.2
+
U2
–
.01 µF
Q1 (1N2907A)
V
RBF
2.2 µF
.01 µF
1
LSB D0
Analog Input
Can Be Either
Force Or Sense
V
EE
V
IN
CLK
50
W
2
50
W
Convert
100116
50
W
50
W
CLK
.01 µF
–2 V
(Analog)
AGND
.01 µF
V
EE
–5.2 V
DGND
.01 µF
–2 V (Digital)
GENERAL DESCRIPTION
The SPT7710 is a fast monolithic 8-bit parallel flash A/D
converter. The nominal conversion rate is 150 MSPS and
the analog bandwidth is in excess of 200 MHz. A major
advance over previous flash converters is the inclusion of
256 input preamplifiers between the reference ladder and
input comparators. (See block diagram.) This not only re-
duces clock transient kickback to the input and reference
ladder due to a low AC beta but also reduces the effect of
the dynamic state of the input signal on the latching char-
acteristics of the input comparators. The preamplifiers act
as buffers and stabilize the input capacitance so that it re-
mains constant for varying input voltages and frequencies
and, therefore, makes the part easier to drive than previ-
ous flash converters. The SPT7710 incorporates a propri-
etary decoding scheme that reduces metastable errors
(sparkle codes or
flyers)
to a maximum of 1 LSB.
The SPT7710 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. Every comparator also has a clock buffer
to reduce differential delays and to improve signal-to-
noise ratio. The output drive capability of the device can
provide full ECL swings into 50
loads.
TYPICAL INTERFACE CIRCUIT
The typical interface circuit is shown in figure 1. The
SPT7710 is relatively easy to apply depending on the
accuracy needed in the intended application. Wire-wrap
may be employed with careful point-to-point ground con-
nections if desired, but to achieve the best operation, a
SPT7710
5
8/17/01